
Eric E. Silverman
Examiner (ID: 15411)
| Most Active Art Unit | 1618 |
| Art Unit(s) | 1618, 1615 |
| Total Applications | 298 |
| Issued Applications | 111 |
| Pending Applications | 2 |
| Abandoned Applications | 185 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4189320
[patent_doc_number] => 06150691
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-21
[patent_title] => 'Spacer patterned, high dielectric constant capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/994849
[patent_app_country] => US
[patent_app_date] => 1997-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 32
[patent_no_of_words] => 4190
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/150/06150691.pdf
[firstpage_image] =>[orig_patent_app_number] => 994849
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/994849 | Spacer patterned, high dielectric constant capacitor | Dec 18, 1997 | Issued |
Array
(
[id] => 3968471
[patent_doc_number] => 05890269
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Semiconductor wafer, handling apparatus, and method'
[patent_app_type] => 1
[patent_app_number] => 8/993339
[patent_app_country] => US
[patent_app_date] => 1997-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 5848
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/890/05890269.pdf
[firstpage_image] =>[orig_patent_app_number] => 993339
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/993339 | Semiconductor wafer, handling apparatus, and method | Dec 18, 1997 | Issued |
Array
(
[id] => 3994336
[patent_doc_number] => 05918133
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-29
[patent_title] => 'Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof'
[patent_app_type] => 1
[patent_app_number] => 8/993029
[patent_app_country] => US
[patent_app_date] => 1997-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3039
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/918/05918133.pdf
[firstpage_image] =>[orig_patent_app_number] => 993029
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/993029 | Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof | Dec 17, 1997 | Issued |
Array
(
[id] => 4258890
[patent_doc_number] => 06258669
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Methods and arrangements for improved formation of control and floating gates in non-volatile memory semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/992960
[patent_app_country] => US
[patent_app_date] => 1997-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 3683
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/258/06258669.pdf
[firstpage_image] =>[orig_patent_app_number] => 992960
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/992960 | Methods and arrangements for improved formation of control and floating gates in non-volatile memory semiconductor devices | Dec 17, 1997 | Issued |
Array
(
[id] => 4246548
[patent_doc_number] => 06136700
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'Method for enhancing the performance of a contact'
[patent_app_type] => 1
[patent_app_number] => 8/992268
[patent_app_country] => US
[patent_app_date] => 1997-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 3273
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/136/06136700.pdf
[firstpage_image] =>[orig_patent_app_number] => 992268
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/992268 | Method for enhancing the performance of a contact | Dec 16, 1997 | Issued |
Array
(
[id] => 4181090
[patent_doc_number] => 06020228
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'CMOS device structure with reduced short channel effect and memory capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/989428
[patent_app_country] => US
[patent_app_date] => 1997-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 79
[patent_figures_cnt] => 79
[patent_no_of_words] => 28816
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 256
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/020/06020228.pdf
[firstpage_image] =>[orig_patent_app_number] => 989428
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/989428 | CMOS device structure with reduced short channel effect and memory capacitor | Dec 11, 1997 | Issued |
Array
(
[id] => 4002923
[patent_doc_number] => 06004858
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-21
[patent_title] => 'Methods of forming hemispherical grained silicon (HSG-Si) capacitor structures including protective layers'
[patent_app_type] => 1
[patent_app_number] => 8/988858
[patent_app_country] => US
[patent_app_date] => 1997-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2925
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/004/06004858.pdf
[firstpage_image] =>[orig_patent_app_number] => 988858
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/988858 | Methods of forming hemispherical grained silicon (HSG-Si) capacitor structures including protective layers | Dec 10, 1997 | Issued |
Array
(
[id] => 4250106
[patent_doc_number] => 06207529
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-27
[patent_title] => 'Semiconductor wafer,wafer alignment patterns and method of forming wafer alignment patterns'
[patent_app_type] => 1
[patent_app_number] => 8/988853
[patent_app_country] => US
[patent_app_date] => 1997-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 3918
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/207/06207529.pdf
[firstpage_image] =>[orig_patent_app_number] => 988853
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/988853 | Semiconductor wafer,wafer alignment patterns and method of forming wafer alignment patterns | Dec 10, 1997 | Issued |
Array
(
[id] => 4347591
[patent_doc_number] => 06214658
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-10
[patent_title] => 'Self-aligned contact structure and method'
[patent_app_type] => 1
[patent_app_number] => 8/987507
[patent_app_country] => US
[patent_app_date] => 1997-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 2160
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/214/06214658.pdf
[firstpage_image] =>[orig_patent_app_number] => 987507
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/987507 | Self-aligned contact structure and method | Dec 8, 1997 | Issued |
Array
(
[id] => 4057100
[patent_doc_number] => 05895238
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-20
[patent_title] => 'Doping technique for MOS devices'
[patent_app_type] => 1
[patent_app_number] => 8/987747
[patent_app_country] => US
[patent_app_date] => 1997-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 5
[patent_no_of_words] => 3745
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/895/05895238.pdf
[firstpage_image] =>[orig_patent_app_number] => 987747
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/987747 | Doping technique for MOS devices | Dec 8, 1997 | Issued |
Array
(
[id] => 4203644
[patent_doc_number] => 06013947
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-11
[patent_title] => 'Substrate having gate recesses or slots and molding device and molding method thereof'
[patent_app_type] => 1
[patent_app_number] => 8/986929
[patent_app_country] => US
[patent_app_date] => 1997-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 1581
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/013/06013947.pdf
[firstpage_image] =>[orig_patent_app_number] => 986929
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/986929 | Substrate having gate recesses or slots and molding device and molding method thereof | Dec 7, 1997 | Issued |
Array
(
[id] => 3896602
[patent_doc_number] => 05897363
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-27
[patent_title] => 'Shallow junction formation using multiple implant sources'
[patent_app_type] => 1
[patent_app_number] => 8/982809
[patent_app_country] => US
[patent_app_date] => 1997-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 3805
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/897/05897363.pdf
[firstpage_image] =>[orig_patent_app_number] => 982809
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/982809 | Shallow junction formation using multiple implant sources | Dec 1, 1997 | Issued |
Array
(
[id] => 4419424
[patent_doc_number] => 06177311
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-23
[patent_title] => 'Method for making a floating gate memory with improved interpoly dielectric'
[patent_app_type] => 1
[patent_app_number] => 8/977868
[patent_app_country] => US
[patent_app_date] => 1997-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2471
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/177/06177311.pdf
[firstpage_image] =>[orig_patent_app_number] => 977868
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/977868 | Method for making a floating gate memory with improved interpoly dielectric | Nov 24, 1997 | Issued |
Array
(
[id] => 4106873
[patent_doc_number] => 06022797
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-08
[patent_title] => 'Method of manufacturing through holes in a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/977347
[patent_app_country] => US
[patent_app_date] => 1997-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
[patent_figures_cnt] => 54
[patent_no_of_words] => 15606
[patent_no_of_claims] => 49
[patent_no_of_ind_claims] => 14
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/022/06022797.pdf
[firstpage_image] =>[orig_patent_app_number] => 977347
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/977347 | Method of manufacturing through holes in a semiconductor device | Nov 23, 1997 | Issued |
Array
(
[id] => 4141626
[patent_doc_number] => 06030867
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-29
[patent_title] => 'Method of fabricating a Fin/HSG DRAM cell capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/975708
[patent_app_country] => US
[patent_app_date] => 1997-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 5258
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 260
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/030/06030867.pdf
[firstpage_image] =>[orig_patent_app_number] => 975708
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/975708 | Method of fabricating a Fin/HSG DRAM cell capacitor | Nov 20, 1997 | Issued |
Array
(
[id] => 4050630
[patent_doc_number] => 05943584
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-24
[patent_title] => 'Annealing methods of doping electrode surfaces using dopant gases'
[patent_app_type] => 1
[patent_app_number] => 8/976338
[patent_app_country] => US
[patent_app_date] => 1997-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3080
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/943/05943584.pdf
[firstpage_image] =>[orig_patent_app_number] => 976338
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/976338 | Annealing methods of doping electrode surfaces using dopant gases | Nov 20, 1997 | Issued |
Array
(
[id] => 4089524
[patent_doc_number] => 06163053
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'Semiconductor device having opposite-polarity region under channel'
[patent_app_type] => 1
[patent_app_number] => 8/964558
[patent_app_country] => US
[patent_app_date] => 1997-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 30
[patent_no_of_words] => 6237
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/163/06163053.pdf
[firstpage_image] =>[orig_patent_app_number] => 964558
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/964558 | Semiconductor device having opposite-polarity region under channel | Nov 4, 1997 | Issued |
Array
(
[id] => 4239092
[patent_doc_number] => 06118148
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => 1
[patent_app_number] => 8/963977
[patent_app_country] => US
[patent_app_date] => 1997-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 37
[patent_no_of_words] => 7523
[patent_no_of_claims] => 77
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/118/06118148.pdf
[firstpage_image] =>[orig_patent_app_number] => 963977
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/963977 | Semiconductor device and manufacturing method thereof | Nov 3, 1997 | Issued |
Array
(
[id] => 3938118
[patent_doc_number] => 05872034
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-16
[patent_title] => 'EPROM in double poly high density CMOS'
[patent_app_type] => 1
[patent_app_number] => 8/963489
[patent_app_country] => US
[patent_app_date] => 1997-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 23
[patent_no_of_words] => 9812
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 248
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/872/05872034.pdf
[firstpage_image] =>[orig_patent_app_number] => 963489
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/963489 | EPROM in double poly high density CMOS | Nov 2, 1997 | Issued |
Array
(
[id] => 4070528
[patent_doc_number] => 05970348
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Read-only memory and corresponding method of manufacturing by MOS technology'
[patent_app_type] => 1
[patent_app_number] => 8/962398
[patent_app_country] => US
[patent_app_date] => 1997-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2403
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/970/05970348.pdf
[firstpage_image] =>[orig_patent_app_number] => 962398
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/962398 | Read-only memory and corresponding method of manufacturing by MOS technology | Oct 30, 1997 | Issued |