
Eric E. Silverman
Examiner (ID: 15411)
| Most Active Art Unit | 1618 |
| Art Unit(s) | 1618, 1615 |
| Total Applications | 298 |
| Issued Applications | 111 |
| Pending Applications | 2 |
| Abandoned Applications | 185 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4039040
[patent_doc_number] => 05926719
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Method for fabricating a crown shaped capacitor structure'
[patent_app_type] => 1
[patent_app_number] => 8/960137
[patent_app_country] => US
[patent_app_date] => 1997-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2812
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 243
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/926/05926719.pdf
[firstpage_image] =>[orig_patent_app_number] => 960137
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/960137 | Method for fabricating a crown shaped capacitor structure | Oct 28, 1997 | Issued |
Array
(
[id] => 4139218
[patent_doc_number] => 06060358
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'Damascene NVRAM cell and method of manufacture'
[patent_app_type] => 1
[patent_app_number] => 8/955209
[patent_app_country] => US
[patent_app_date] => 1997-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 36
[patent_no_of_words] => 5587
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/060/06060358.pdf
[firstpage_image] =>[orig_patent_app_number] => 955209
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/955209 | Damascene NVRAM cell and method of manufacture | Oct 20, 1997 | Issued |
Array
(
[id] => 1486717
[patent_doc_number] => 06365933
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-02
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => B1
[patent_app_number] => 08/951819
[patent_app_country] => US
[patent_app_date] => 1997-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 43
[patent_no_of_words] => 15094
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/365/06365933.pdf
[firstpage_image] =>[orig_patent_app_number] => 08951819
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/951819 | Semiconductor device and method of manufacturing the same | Oct 13, 1997 | Issued |
Array
(
[id] => 4002767
[patent_doc_number] => 05986314
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Depletion mode MOS capacitor with patterned V.sub.t implants'
[patent_app_type] => 1
[patent_app_number] => 8/947209
[patent_app_country] => US
[patent_app_date] => 1997-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 2667
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/986/05986314.pdf
[firstpage_image] =>[orig_patent_app_number] => 947209
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/947209 | Depletion mode MOS capacitor with patterned V.sub.t implants | Oct 7, 1997 | Issued |
| 08/939209 | METHOD AND APPARATUS FOR MINIMIZING DOPANT OUTDIFFUSION IN GATE STRUCTURES | Sep 28, 1997 | Abandoned |
Array
(
[id] => 4049092
[patent_doc_number] => 05912481
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-15
[patent_title] => 'Heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction'
[patent_app_type] => 1
[patent_app_number] => 8/939487
[patent_app_country] => US
[patent_app_date] => 1997-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3996
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/912/05912481.pdf
[firstpage_image] =>[orig_patent_app_number] => 939487
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/939487 | Heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction | Sep 28, 1997 | Issued |
Array
(
[id] => 4070273
[patent_doc_number] => 05970334
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Method of manufacturing contacts to diverse doped regions using intermediate layer of arsenic or phosphorus'
[patent_app_type] => 1
[patent_app_number] => 8/938709
[patent_app_country] => US
[patent_app_date] => 1997-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 4425
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/970/05970334.pdf
[firstpage_image] =>[orig_patent_app_number] => 938709
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/938709 | Method of manufacturing contacts to diverse doped regions using intermediate layer of arsenic or phosphorus | Sep 25, 1997 | Issued |
Array
(
[id] => 3938238
[patent_doc_number] => 05872041
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-16
[patent_title] => 'Method for fabricating electrodes of a semiconductor capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/933008
[patent_app_country] => US
[patent_app_date] => 1997-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 1902
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/872/05872041.pdf
[firstpage_image] =>[orig_patent_app_number] => 933008
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/933008 | Method for fabricating electrodes of a semiconductor capacitor | Sep 17, 1997 | Issued |
Array
(
[id] => 4057768
[patent_doc_number] => 05909615
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-01
[patent_title] => 'Method for making a vertically redundant dual thin film transistor'
[patent_app_type] => 1
[patent_app_number] => 8/929925
[patent_app_country] => US
[patent_app_date] => 1997-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2327
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 313
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/909/05909615.pdf
[firstpage_image] =>[orig_patent_app_number] => 929925
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/929925 | Method for making a vertically redundant dual thin film transistor | Sep 14, 1997 | Issued |
Array
(
[id] => 3991075
[patent_doc_number] => 05891781
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Method for coding mask read-only memory'
[patent_app_type] => 1
[patent_app_number] => 8/924318
[patent_app_country] => US
[patent_app_date] => 1997-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 1773
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/891/05891781.pdf
[firstpage_image] =>[orig_patent_app_number] => 924318
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/924318 | Method for coding mask read-only memory | Sep 4, 1997 | Issued |
Array
(
[id] => 3937058
[patent_doc_number] => 05915189
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-22
[patent_title] => 'Manufacturing method for semiconductor memory device having a storage node with surface irregularities'
[patent_app_type] => 1
[patent_app_number] => 8/918619
[patent_app_country] => US
[patent_app_date] => 1997-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 2684
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/915/05915189.pdf
[firstpage_image] =>[orig_patent_app_number] => 918619
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/918619 | Manufacturing method for semiconductor memory device having a storage node with surface irregularities | Aug 21, 1997 | Issued |
Array
(
[id] => 4084411
[patent_doc_number] => 06025218
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'Method of manufacturing a thin-film electronic device with a laminated conductor'
[patent_app_type] => 1
[patent_app_number] => 8/916775
[patent_app_country] => US
[patent_app_date] => 1997-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 5159
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/025/06025218.pdf
[firstpage_image] =>[orig_patent_app_number] => 916775
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/916775 | Method of manufacturing a thin-film electronic device with a laminated conductor | Aug 19, 1997 | Issued |
Array
(
[id] => 4368462
[patent_doc_number] => 06287900
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-11
[patent_title] => 'Semiconductor device with catalyst addition and removal'
[patent_app_type] => 1
[patent_app_number] => 8/912975
[patent_app_country] => US
[patent_app_date] => 1997-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 76
[patent_no_of_words] => 14692
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/287/06287900.pdf
[firstpage_image] =>[orig_patent_app_number] => 912975
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/912975 | Semiconductor device with catalyst addition and removal | Aug 12, 1997 | Issued |
Array
(
[id] => 4067472
[patent_doc_number] => 05895934
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-20
[patent_title] => 'Negative differential resistance device based on tunneling through microclusters, and method therefor'
[patent_app_type] => 1
[patent_app_number] => 8/915547
[patent_app_country] => US
[patent_app_date] => 1997-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1131
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 53
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/895/05895934.pdf
[firstpage_image] =>[orig_patent_app_number] => 915547
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/915547 | Negative differential resistance device based on tunneling through microclusters, and method therefor | Aug 12, 1997 | Issued |
Array
(
[id] => 4206457
[patent_doc_number] => 06027964
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-22
[patent_title] => 'Method of making an IGFET with a selectively doped gate in combination with a protected resistor'
[patent_app_type] => 1
[patent_app_number] => 8/905681
[patent_app_country] => US
[patent_app_date] => 1997-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 30
[patent_no_of_words] => 7338
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/027/06027964.pdf
[firstpage_image] =>[orig_patent_app_number] => 905681
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/905681 | Method of making an IGFET with a selectively doped gate in combination with a protected resistor | Aug 3, 1997 | Issued |
Array
(
[id] => 4106679
[patent_doc_number] => 06022783
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-08
[patent_title] => 'NMOS field effect transistors and methods of forming NMOS field effect transistors'
[patent_app_type] => 1
[patent_app_number] => 8/902763
[patent_app_country] => US
[patent_app_date] => 1997-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2374
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/022/06022783.pdf
[firstpage_image] =>[orig_patent_app_number] => 902763
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/902763 | NMOS field effect transistors and methods of forming NMOS field effect transistors | Jul 29, 1997 | Issued |
Array
(
[id] => 3956965
[patent_doc_number] => 05930605
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'Compact self-aligned body contact silicon-on-insulator transistors'
[patent_app_type] => 1
[patent_app_number] => 8/895328
[patent_app_country] => US
[patent_app_date] => 1997-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 22
[patent_no_of_words] => 4308
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/930/05930605.pdf
[firstpage_image] =>[orig_patent_app_number] => 895328
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/895328 | Compact self-aligned body contact silicon-on-insulator transistors | Jul 15, 1997 | Issued |
Array
(
[id] => 3967095
[patent_doc_number] => 05956595
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-21
[patent_title] => 'Method of fabricating a semiconductor integrated circuit having a capacitor with lower electrode comprising titanium nitride'
[patent_app_type] => 1
[patent_app_number] => 8/892999
[patent_app_country] => US
[patent_app_date] => 1997-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 3470
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[pdf_file] => patents/05/956/05956595.pdf
[firstpage_image] =>[orig_patent_app_number] => 892999
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/892999 | Method of fabricating a semiconductor integrated circuit having a capacitor with lower electrode comprising titanium nitride | Jul 14, 1997 | Issued |
Array
(
[id] => 4062607
[patent_doc_number] => 05866445
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-02
[patent_title] => 'High density CMOS circuit with split gate oxide'
[patent_app_type] => 1
[patent_app_number] => 8/893817
[patent_app_country] => US
[patent_app_date] => 1997-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/866/05866445.pdf
[firstpage_image] =>[orig_patent_app_number] => 893817
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/893817 | High density CMOS circuit with split gate oxide | Jul 10, 1997 | Issued |
Array
(
[id] => 3937420
[patent_doc_number] => 05981345
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Si/SiGe MOSFET and method for fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 8/891013
[patent_app_country] => US
[patent_app_date] => 1997-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/981/05981345.pdf
[firstpage_image] =>[orig_patent_app_number] => 891013
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/891013 | Si/SiGe MOSFET and method for fabricating the same | Jul 9, 1997 | Issued |