Search

Eric E. Silverman

Examiner (ID: 15411)

Most Active Art Unit
1618
Art Unit(s)
1618, 1615
Total Applications
298
Issued Applications
111
Pending Applications
2
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10252321 [patent_doc_number] => 20150137317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'SEMICONDUCTOR WAFER, METHOD OF PRODUCING A SEMICONDUCTOR WAFER AND METHOD OF PRODUCING A COMPOSITE WAFER' [patent_app_type] => utility [patent_app_number] => 14/568165 [patent_app_country] => US [patent_app_date] => 2014-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7739 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14568165 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/568165
SEMICONDUCTOR WAFER, METHOD OF PRODUCING A SEMICONDUCTOR WAFER AND METHOD OF PRODUCING A COMPOSITE WAFER Dec 11, 2014 Abandoned
Array ( [id] => 10189592 [patent_doc_number] => 09219021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'Semiconductor device including heat dissipating structure' [patent_app_type] => utility [patent_app_number] => 14/558638 [patent_app_country] => US [patent_app_date] => 2014-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 11043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14558638 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/558638
Semiconductor device including heat dissipating structure Dec 1, 2014 Issued
Array ( [id] => 10508481 [patent_doc_number] => 09236357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-12 [patent_title] => 'Mounting substrate and light emitting device' [patent_app_type] => utility [patent_app_number] => 14/556404 [patent_app_country] => US [patent_app_date] => 2014-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 8312 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14556404 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/556404
Mounting substrate and light emitting device Nov 30, 2014 Issued
Array ( [id] => 9928494 [patent_doc_number] => 20150076686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'Chip Stacking Packaging Structure' [patent_app_type] => utility [patent_app_number] => 14/552674 [patent_app_country] => US [patent_app_date] => 2014-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3920 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14552674 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/552674
Chip stacking packaging structure Nov 24, 2014 Issued
Array ( [id] => 10765315 [patent_doc_number] => 20160111471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'SiC-Si3N4 Nanolaminates as a Semiconductor for MSM Snapback Selector Devices' [patent_app_type] => utility [patent_app_number] => 14/516273 [patent_app_country] => US [patent_app_date] => 2014-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12734 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14516273 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/516273
SiC—Si3N4 nanolaminates as a semiconductor for MSM snapback selector devices Oct 15, 2014 Issued
Array ( [id] => 9809830 [patent_doc_number] => 20150021775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND APPARATUS FOR PRODUCING SEMICONDUCTOR' [patent_app_type] => utility [patent_app_number] => 14/510388 [patent_app_country] => US [patent_app_date] => 2014-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 14720 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14510388 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/510388
Method for manufacturing semiconductor device for forming metal element-containing layer on insulating layer in which concave portion is formed, semiconductor device including insulating layer in which concave portion is formed, and semiconductor layer on insulating layer in which concave portion is formed Oct 8, 2014 Issued
Array ( [id] => 11079505 [patent_doc_number] => 20160276470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'INSULATED GATE BIPOLAR TRANSISTOR AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 15/034944 [patent_app_country] => US [patent_app_date] => 2014-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6708 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15034944 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/034944
Insulated gate bipolar transistor and method for manufacturing same Oct 5, 2014 Issued
Array ( [id] => 9839357 [patent_doc_number] => 20150031438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-29 [patent_title] => 'METHOD OF SIMULTANEOUS INDICATION OF MULTIPLE WINNING COMBINATIONS IN A SYMBOL MATRIX' [patent_app_type] => utility [patent_app_number] => 14/505803 [patent_app_country] => US [patent_app_date] => 2014-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3278 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14505803 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/505803
Method of simultaneous indication of multiple winning combinations in a symbol matrix Oct 2, 2014 Issued
Array ( [id] => 10060105 [patent_doc_number] => 09099469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'E-fuse structure of semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/503563 [patent_app_country] => US [patent_app_date] => 2014-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 48 [patent_no_of_words] => 15742 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14503563 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/503563
E-fuse structure of semiconductor device Sep 30, 2014 Issued
Array ( [id] => 10165480 [patent_doc_number] => 09196714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'IGBT device with buried emitter regions' [patent_app_type] => utility [patent_app_number] => 14/496937 [patent_app_country] => US [patent_app_date] => 2014-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5218 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14496937 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/496937
IGBT device with buried emitter regions Sep 24, 2014 Issued
Array ( [id] => 9802836 [patent_doc_number] => 20150014781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-15 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/489188 [patent_app_country] => US [patent_app_date] => 2014-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3498 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14489188 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/489188
Semiconductor device including a local wiring connecting diffusion regions Sep 16, 2014 Issued
Array ( [id] => 12554781 [patent_doc_number] => 10014487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Organic electroluminescent device [patent_app_type] => utility [patent_app_number] => 15/022244 [patent_app_country] => US [patent_app_date] => 2014-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 14066 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15022244 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/022244
Organic electroluminescent device Sep 11, 2014 Issued
Array ( [id] => 9958486 [patent_doc_number] => 09006696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-14 [patent_title] => 'Metal aluminum nitride embedded resistors for resistive random memory access cells' [patent_app_type] => utility [patent_app_number] => 14/480025 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 9196 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14480025 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/480025
Metal aluminum nitride embedded resistors for resistive random memory access cells Sep 7, 2014 Issued
Array ( [id] => 9932030 [patent_doc_number] => 20150080223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'SEMICONDUCTOR DEVICE, SUPERCONDUCTING DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/475846 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5646 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475846 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/475846
Semiconductor device, superconducting device, and manufacturing method of semiconductor device Sep 2, 2014 Issued
Array ( [id] => 11824831 [patent_doc_number] => 20170213768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'TECHNIQUE FOR FILLING HIGH ASPECT RATIO, NARROW STRUCTURES WITH MULTIPLE METAL LAYERS AND ASSOCIATED CONFIGURATIONS' [patent_app_type] => utility [patent_app_number] => 15/328473 [patent_app_country] => US [patent_app_date] => 2014-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8713 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15328473 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/328473
Technique for filling high aspect ratio, narrow structures with multiple metal layers and associated configurations Aug 28, 2014 Issued
Array ( [id] => 10958420 [patent_doc_number] => 20140361445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 14/470076 [patent_app_country] => US [patent_app_date] => 2014-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5211 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14470076 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/470076
Semiconductor device and method for manufacturing same Aug 26, 2014 Issued
Array ( [id] => 10100108 [patent_doc_number] => 09136429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Multilayer construction' [patent_app_type] => utility [patent_app_number] => 14/467497 [patent_app_country] => US [patent_app_date] => 2014-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 8204 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14467497 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/467497
Multilayer construction Aug 24, 2014 Issued
Array ( [id] => 11615724 [patent_doc_number] => 09653588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'GaN substrate, semiconductor device and method for fabricating GaN substrate and semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/466295 [patent_app_country] => US [patent_app_date] => 2014-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5539 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14466295 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/466295
GaN substrate, semiconductor device and method for fabricating GaN substrate and semiconductor device Aug 21, 2014 Issued
Array ( [id] => 10958411 [patent_doc_number] => 20140361436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'SEMICONDUCTOR DEVICE MANUFACTURING METHOD, STORAGE MEDIUM AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/464875 [patent_app_country] => US [patent_app_date] => 2014-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7311 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464875 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/464875
Semiconductor device manufacturing method for suppresing wiring material from being diffused into insulating film, storage medium and semiconductor device Aug 20, 2014 Issued
Array ( [id] => 9792862 [patent_doc_number] => 20150004806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'LOW-K OXIDE DEPOSITION BY HYDROLYSIS AND CONDENSATION' [patent_app_type] => utility [patent_app_number] => 14/464196 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464196 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/464196
Low-K oxide deposition by hydrolysis and condensation Aug 19, 2014 Issued
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