Search

Eric E. Silverman

Examiner (ID: 15411)

Most Active Art Unit
1618
Art Unit(s)
1618, 1615
Total Applications
298
Issued Applications
111
Pending Applications
2
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9195173 [patent_doc_number] => 20130334488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'VERTICAL MEMORY DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/845959 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 7189 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13845959 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/845959
Vertical memory device and method of fabricating the same Mar 17, 2013 Issued
Array ( [id] => 9542523 [patent_doc_number] => 20140167170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND SEMICONDUCTOR STRUCTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 13/845062 [patent_app_country] => US [patent_app_date] => 2013-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3472 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13845062 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/845062
ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND SEMICONDUCTOR STRUCTURE THEREOF Mar 16, 2013 Abandoned
Array ( [id] => 9728891 [patent_doc_number] => 20140264598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'STRESS ENHANCED FINFET DEVICES' [patent_app_type] => utility [patent_app_number] => 13/840069 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5241 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13840069 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/840069
Stress enhanced finFET devices Mar 14, 2013 Issued
Array ( [id] => 9778454 [patent_doc_number] => 08853661 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-07 [patent_title] => 'Metal aluminum nitride embedded resistors for resistive random memory access cells' [patent_app_type] => utility [patent_app_number] => 13/835256 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 9164 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13835256 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/835256
Metal aluminum nitride embedded resistors for resistive random memory access cells Mar 14, 2013 Issued
Array ( [id] => 9704537 [patent_doc_number] => 08829606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-09 [patent_title] => 'Ditches near semiconductor fins and methods for forming the same' [patent_app_type] => utility [patent_app_number] => 13/838407 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13838407 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/838407
Ditches near semiconductor fins and methods for forming the same Mar 14, 2013 Issued
Array ( [id] => 9778556 [patent_doc_number] => 08853764 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-07 [patent_title] => 'Integration of low Rdson LDMOS with high sheet resistance poly resistor' [patent_app_type] => utility [patent_app_number] => 13/832682 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3529 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13832682 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/832682
Integration of low Rdson LDMOS with high sheet resistance poly resistor Mar 14, 2013 Issued
Array ( [id] => 10888071 [patent_doc_number] => 08912066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Lateral double-diffused high voltage device' [patent_app_type] => utility [patent_app_number] => 13/831981 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6459 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13831981 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/831981
Lateral double-diffused high voltage device Mar 14, 2013 Issued
Array ( [id] => 10876740 [patent_doc_number] => 08901529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-02 [patent_title] => 'Memory array with self-aligned epitaxially grown memory elements and annular FET' [patent_app_type] => utility [patent_app_number] => 13/834998 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3686 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13834998 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/834998
Memory array with self-aligned epitaxially grown memory elements and annular FET Mar 14, 2013 Issued
Array ( [id] => 9711314 [patent_doc_number] => 08835889 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-16 [patent_title] => 'Parallel shunt paths in thermally assisted magnetic memory cells' [patent_app_type] => utility [patent_app_number] => 13/800966 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3082 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13800966 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/800966
Parallel shunt paths in thermally assisted magnetic memory cells Mar 12, 2013 Issued
Array ( [id] => 9728846 [patent_doc_number] => 20140264553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD OF FABRICATING MONOS SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/798393 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13798393 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/798393
Method of fabricating MONOS semiconductor device Mar 12, 2013 Issued
Array ( [id] => 9662843 [patent_doc_number] => 08809827 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-19 [patent_title] => 'Thermally assisted MRAM with multilayer strap and top contact for low thermal conductivity' [patent_app_type] => utility [patent_app_number] => 13/799148 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13799148 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/799148
Thermally assisted MRAM with multilayer strap and top contact for low thermal conductivity Mar 12, 2013 Issued
Array ( [id] => 10053548 [patent_doc_number] => 09093435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Package-on-package assembly with wire bonds to encapsulation surface' [patent_app_type] => utility [patent_app_number] => 13/792521 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 39 [patent_no_of_words] => 15588 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792521 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/792521
Package-on-package assembly with wire bonds to encapsulation surface Mar 10, 2013 Issued
Array ( [id] => 10053548 [patent_doc_number] => 09093435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Package-on-package assembly with wire bonds to encapsulation surface' [patent_app_type] => utility [patent_app_number] => 13/792521 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 39 [patent_no_of_words] => 15588 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792521 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/792521
Package-on-package assembly with wire bonds to encapsulation surface Mar 10, 2013 Issued
Array ( [id] => 10053548 [patent_doc_number] => 09093435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Package-on-package assembly with wire bonds to encapsulation surface' [patent_app_type] => utility [patent_app_number] => 13/792521 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 39 [patent_no_of_words] => 15588 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792521 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/792521
Package-on-package assembly with wire bonds to encapsulation surface Mar 10, 2013 Issued
Array ( [id] => 10053548 [patent_doc_number] => 09093435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Package-on-package assembly with wire bonds to encapsulation surface' [patent_app_type] => utility [patent_app_number] => 13/792521 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 39 [patent_no_of_words] => 15588 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792521 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/792521
Package-on-package assembly with wire bonds to encapsulation surface Mar 10, 2013 Issued
Array ( [id] => 10838570 [patent_doc_number] => 08866250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Multiple metal film stack in BSI chips' [patent_app_type] => utility [patent_app_number] => 13/789820 [patent_app_country] => US [patent_app_date] => 2013-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6351 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13789820 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/789820
Multiple metal film stack in BSI chips Mar 7, 2013 Issued
Array ( [id] => 8913876 [patent_doc_number] => 20130175501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'Pulsed Growth of Catalyst-Free Growth of GaN Nanowires and Application in Group III Nitride Semiconductor Bulk Material' [patent_app_type] => utility [patent_app_number] => 13/783219 [patent_app_country] => US [patent_app_date] => 2013-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12507 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13783219 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/783219
Pulsed growth of catalyst-free growth of GaN nanowires and application in group III nitride semiconductor bulk material Feb 28, 2013 Issued
Array ( [id] => 9869203 [patent_doc_number] => 08956975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Electroless plated material formed directly on metal' [patent_app_type] => utility [patent_app_number] => 13/781022 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6036 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13781022 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/781022
Electroless plated material formed directly on metal Feb 27, 2013 Issued
Array ( [id] => 9330595 [patent_doc_number] => 20140057377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'METHOD FOR MANUFACTURING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/115073 [patent_app_country] => US [patent_app_date] => 2013-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4811 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14115073 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/115073
Method for manufacturing device Feb 17, 2013 Issued
Array ( [id] => 9441462 [patent_doc_number] => 08710575 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-29 [patent_title] => 'Semiconductor device, integrated circuit and method of manufacturing an integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/754997 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6691 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13754997 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/754997
Semiconductor device, integrated circuit and method of manufacturing an integrated circuit Jan 30, 2013 Issued
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