Eric E. Silverman

Array ( [id] => 6270887 [patent_doc_number] => 20100116811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'GRILL' [patent_app_type] => utility [patent_app_number] => 12/616769 [patent_app_country] => US [patent_app_date] => 2009-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1413 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20100116811.pdf [firstpage_image] =>[orig_patent_app_number] => 12616769 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8859031 [patent_doc_number] => 08461566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'Methods, structures and devices for increasing memory density' [patent_app_type] => utility [patent_app_number] => 12/610922 [patent_app_country] => US [patent_app_date] => 2009-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 66 [patent_no_of_words] => 11642 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12610922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6272113 [patent_doc_number] => 20100117187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'METHOD FOR FORMING GATE IN FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/609374 [patent_app_country] => US [patent_app_date] => 2009-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2036 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20100117187.pdf [firstpage_image] =>[orig_patent_app_number] => 12609374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4639479 [patent_doc_number] => 08017506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Semiconductor device and method for forming the same' [patent_app_type] => utility [patent_app_number] => 12/604879 [patent_app_country] => US [patent_app_date] => 2009-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 62 [patent_no_of_words] => 15213 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/017/08017506.pdf [firstpage_image] =>[orig_patent_app_number] => 12604879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6473322 [patent_doc_number] => 20100041176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'PATTERNED ASSEMBLY FOR MANUFACTURING A SOLAR CELL AND A METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/603707 [patent_app_country] => US [patent_app_date] => 2009-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20100041176.pdf [firstpage_image] =>[orig_patent_app_number] => 12603707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7685900 [patent_doc_number] => 20100120241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/579137 [patent_app_country] => US [patent_app_date] => 2009-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4959 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20100120241.pdf [firstpage_image] =>[orig_patent_app_number] => 12579137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6231335 [patent_doc_number] => 20100264532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'ELECTRONIC DEVICE PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/579187 [patent_app_country] => US [patent_app_date] => 2009-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6294 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20100264532.pdf [firstpage_image] =>[orig_patent_app_number] => 12579187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8533220 [patent_doc_number] => 08309374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Advanced platform for processing crystalline silicon solar cells' [patent_app_type] => utility [patent_app_number] => 12/575088 [patent_app_country] => US [patent_app_date] => 2009-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 11890 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12575088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6537663 [patent_doc_number] => 20100015737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, AND METHOD OF MANUFACTURING BASE MATERIAL' [patent_app_type] => utility [patent_app_number] => 12/566040 [patent_app_country] => US [patent_app_date] => 2009-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12499 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20100015737.pdf [firstpage_image] =>[orig_patent_app_number] => 12566040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8139883 [patent_doc_number] => 20120094496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'Process For Locally Dissolving The Oxide Layer In A Semiconductor-On-Insulator Type Structure' [patent_app_type] => utility [patent_app_number] => 13/062996 [patent_app_country] => US [patent_app_date] => 2009-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5408 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20120094496.pdf [firstpage_image] =>[orig_patent_app_number] => 13062996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4605058 [patent_doc_number] => 07986039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Wafer assembly comprising MEMS wafer with polymerized siloxane attachment surface' [patent_app_type] => utility [patent_app_number] => 12/563956 [patent_app_country] => US [patent_app_date] => 2009-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 47 [patent_no_of_words] => 10795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/986/07986039.pdf [firstpage_image] =>[orig_patent_app_number] => 12563956 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8543308 [patent_doc_number] => 08318598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Contacts and vias of a semiconductor device formed by a hard mask and double exposure' [patent_app_type] => utility [patent_app_number] => 12/537321 [patent_app_country] => US [patent_app_date] => 2009-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 9376 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12537321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8969085 [patent_doc_number] => 08507899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-13 [patent_title] => 'Electric transport component, method of manufacturing the same, as well as electro-optical device and opto-electrical device' [patent_app_type] => utility [patent_app_number] => 13/056418 [patent_app_country] => US [patent_app_date] => 2009-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5474 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13056418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8749932 [patent_doc_number] => 08415766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Process for smoothening III-N substrates' [patent_app_type] => utility [patent_app_number] => 12/511514 [patent_app_country] => US [patent_app_date] => 2009-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4552 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12511514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6149369 [patent_doc_number] => 20110020964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'METHOD OF FABRICATING INKJET PRINTHEAD ASSEMBLY HAVING BACKSIDE ELECTRICAL CONNECTIONS' [patent_app_type] => utility [patent_app_number] => 12/509490 [patent_app_country] => US [patent_app_date] => 2009-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7811 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20110020964.pdf [firstpage_image] =>[orig_patent_app_number] => 12509490 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6419477 [patent_doc_number] => 20100167539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'METHOD FOR INSULATING WIRES OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/491883 [patent_app_country] => US [patent_app_date] => 2009-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4619 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20100167539.pdf [firstpage_image] =>[orig_patent_app_number] => 12491883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6419073 [patent_doc_number] => 20100167483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'METHOD FOR FABRICATING PMOS TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 12/491983 [patent_app_country] => US [patent_app_date] => 2009-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2884 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20100167483.pdf [firstpage_image] =>[orig_patent_app_number] => 12491983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5465126 [patent_doc_number] => 20090325326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'Apparatus and method for manufacturing semiconductor devices through layer material dimension analysis' [patent_app_type] => utility [patent_app_number] => 12/457873 [patent_app_country] => US [patent_app_date] => 2009-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 8694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12457873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4571360 [patent_doc_number] => 07829432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Method for manufacturing SOI substrate' [patent_app_type] => utility [patent_app_number] => 12/489594 [patent_app_country] => US [patent_app_date] => 2009-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 51 [patent_no_of_words] => 18374 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/829/07829432.pdf [firstpage_image] =>[orig_patent_app_number] => 12489594 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6293288 [patent_doc_number] => 20100159711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'PRECURSOR ADDITION TO SILICON OXIDE CVD FOR IMPROVED LOW TEMPERATURE GAPFILL' [patent_app_type] => utility [patent_app_number] => 12/489234 [patent_app_country] => US [patent_app_date] => 2009-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6237 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20100159711.pdf [firstpage_image] =>[orig_patent_app_number] => 12489234 [rel_patent_id] =>[rel_patent_doc_number] =>)