Search

Eric E. Silverman

Examiner (ID: 15411)

Most Active Art Unit
1618
Art Unit(s)
1618, 1615
Total Applications
298
Issued Applications
111
Pending Applications
2
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4845972 [patent_doc_number] => 20080182380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/970583 [patent_app_country] => US [patent_app_date] => 2008-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5247 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20080182380.pdf [firstpage_image] =>[orig_patent_app_number] => 11970583 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/970583
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Jan 7, 2008 Abandoned
Array ( [id] => 5581002 [patent_doc_number] => 20090176348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'REMOVABLE LAYER MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 11/969604 [patent_app_country] => US [patent_app_date] => 2008-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20090176348.pdf [firstpage_image] =>[orig_patent_app_number] => 11969604 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/969604
Removable layer manufacturing method Jan 3, 2008 Issued
Array ( [id] => 7530392 [patent_doc_number] => 07842614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Method for manufacturing semiconductor device and polisher used in the method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/968933 [patent_app_country] => US [patent_app_date] => 2008-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6296 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/842/07842614.pdf [firstpage_image] =>[orig_patent_app_number] => 11968933 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/968933
Method for manufacturing semiconductor device and polisher used in the method for manufacturing semiconductor device Jan 2, 2008 Issued
Array ( [id] => 5349476 [patent_doc_number] => 20090004837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/966194 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2872 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20090004837.pdf [firstpage_image] =>[orig_patent_app_number] => 11966194 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/966194
Method of fabricating semiconductor device Dec 27, 2007 Issued
Array ( [id] => 141933 [patent_doc_number] => 07691718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Dual layer hard mask for block salicide poly resistor (BSR) patterning' [patent_app_type] => utility [patent_app_number] => 12/005944 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1027 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/691/07691718.pdf [firstpage_image] =>[orig_patent_app_number] => 12005944 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/005944
Dual layer hard mask for block salicide poly resistor (BSR) patterning Dec 26, 2007 Issued
Array ( [id] => 4927528 [patent_doc_number] => 20080166891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'HEAT TREATMENT METHOD FOR SILICON WAFER' [patent_app_type] => utility [patent_app_number] => 11/965214 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4774 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20080166891.pdf [firstpage_image] =>[orig_patent_app_number] => 11965214 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/965214
HEAT TREATMENT METHOD FOR SILICON WAFER Dec 26, 2007 Abandoned
Array ( [id] => 4965379 [patent_doc_number] => 20080108199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'METHOD OF FORMING AN INTEGRATED CIRCUIT INCLUDING A TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 11/963044 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 10342 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20080108199.pdf [firstpage_image] =>[orig_patent_app_number] => 11963044 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/963044
METHOD OF FORMING AN INTEGRATED CIRCUIT INCLUDING A TRANSISTOR Dec 20, 2007 Abandoned
Array ( [id] => 5502353 [patent_doc_number] => 20090163041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'LOW WET ETCH RATE SILICON NITRIDE FILM' [patent_app_type] => utility [patent_app_number] => 11/962674 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7294 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20090163041.pdf [firstpage_image] =>[orig_patent_app_number] => 11962674 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962674
Low wet etch rate silicon nitride film Dec 20, 2007 Issued
Array ( [id] => 32387 [patent_doc_number] => 07790497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Method to prevent alloy formation when forming layered metal oxides by metal oxidation' [patent_app_type] => utility [patent_app_number] => 12/004124 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 2106 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/790/07790497.pdf [firstpage_image] =>[orig_patent_app_number] => 12004124 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/004124
Method to prevent alloy formation when forming layered metal oxides by metal oxidation Dec 19, 2007 Issued
Array ( [id] => 5502320 [patent_doc_number] => 20090163008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'Lithographically Space-Defined Charge Storage Regions In Non-Volatile Memory' [patent_app_type] => utility [patent_app_number] => 11/960513 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 19158 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20090163008.pdf [firstpage_image] =>[orig_patent_app_number] => 11960513 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/960513
Lithographically space-defined charge storage regions in non-volatile memory Dec 18, 2007 Issued
Array ( [id] => 5546082 [patent_doc_number] => 20090155959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Semiconductor Device and Method of Forming Integrated Passive Device Module' [patent_app_type] => utility [patent_app_number] => 11/958603 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5244 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20090155959.pdf [firstpage_image] =>[orig_patent_app_number] => 11958603 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958603
Semiconductor device and method of forming integrated passive device module Dec 17, 2007 Issued
Array ( [id] => 132668 [patent_doc_number] => 07696088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Manufacturing methods of metal wire, electrode and TFT array substrate' [patent_app_type] => utility [patent_app_number] => 11/958634 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 5705 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/696/07696088.pdf [firstpage_image] =>[orig_patent_app_number] => 11958634 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958634
Manufacturing methods of metal wire, electrode and TFT array substrate Dec 17, 2007 Issued
Array ( [id] => 83375 [patent_doc_number] => 07741133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Resistance measurements of a helical coil' [patent_app_type] => utility [patent_app_number] => 11/957484 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 6045 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/741/07741133.pdf [firstpage_image] =>[orig_patent_app_number] => 11957484 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/957484
Resistance measurements of a helical coil Dec 16, 2007 Issued
Array ( [id] => 4752597 [patent_doc_number] => 20080160672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/957233 [patent_app_country] => US [patent_app_date] => 2007-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2589 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20080160672.pdf [firstpage_image] =>[orig_patent_app_number] => 11957233 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/957233
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Dec 13, 2007 Abandoned
Array ( [id] => 32579 [patent_doc_number] => 07790619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Method for fabricating semiconductor device having narrow channel' [patent_app_type] => utility [patent_app_number] => 12/001864 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2036 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/790/07790619.pdf [firstpage_image] =>[orig_patent_app_number] => 12001864 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/001864
Method for fabricating semiconductor device having narrow channel Dec 12, 2007 Issued
Array ( [id] => 4879875 [patent_doc_number] => 20080153258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'PROCESS AND DEVICE FOR BONDING WAFERS' [patent_app_type] => utility [patent_app_number] => 11/953553 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2053 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20080153258.pdf [firstpage_image] =>[orig_patent_app_number] => 11953553 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/953553
Process and device for bonding wafers Dec 9, 2007 Issued
Array ( [id] => 122642 [patent_doc_number] => 07704804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Method of forming a crack stop laser fuse with fixed passivation layer coverage' [patent_app_type] => utility [patent_app_number] => 11/953363 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/704/07704804.pdf [firstpage_image] =>[orig_patent_app_number] => 11953363 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/953363
Method of forming a crack stop laser fuse with fixed passivation layer coverage Dec 9, 2007 Issued
Array ( [id] => 236286 [patent_doc_number] => 07595267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Method of forming contact hole of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/951334 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2160 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/595/07595267.pdf [firstpage_image] =>[orig_patent_app_number] => 11951334 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/951334
Method of forming contact hole of semiconductor device Dec 5, 2007 Issued
Array ( [id] => 4692606 [patent_doc_number] => 20080085377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'PLASMA TREATMENT APPARATUS AND METHOD FOR PLASMA TREATMENT' [patent_app_type] => utility [patent_app_number] => 11/950818 [patent_app_country] => US [patent_app_date] => 2007-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6355 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20080085377.pdf [firstpage_image] =>[orig_patent_app_number] => 11950818 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/950818
Plasma treatment apparatus and method for plasma treatment Dec 4, 2007 Issued
Array ( [id] => 4866946 [patent_doc_number] => 20080146005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'METHODS FOR CREATING A DENSIFIED GROUP IV SEMICONDUCTOR NANOPARTICLE THIN FILM' [patent_app_type] => utility [patent_app_number] => 11/950024 [patent_app_country] => US [patent_app_date] => 2007-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8477 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20080146005.pdf [firstpage_image] =>[orig_patent_app_number] => 11950024 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/950024
Methods for creating a densified group IV semiconductor nanoparticle thin film Dec 3, 2007 Issued
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