Search

Eric E. Silverman

Examiner (ID: 15411)

Most Active Art Unit
1618
Art Unit(s)
1618, 1615
Total Applications
298
Issued Applications
111
Pending Applications
2
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 24792 [patent_doc_number] => 07795615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Capacitor integrated in a structure surrounding a die' [patent_app_type] => utility [patent_app_number] => 11/268854 [patent_app_country] => US [patent_app_date] => 2005-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4274 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/795/07795615.pdf [firstpage_image] =>[orig_patent_app_number] => 11268854 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/268854
Capacitor integrated in a structure surrounding a die Nov 7, 2005 Issued
Array ( [id] => 587603 [patent_doc_number] => 07439197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'Method of fabricating a capacitor' [patent_app_type] => utility [patent_app_number] => 11/267264 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2891 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/439/07439197.pdf [firstpage_image] =>[orig_patent_app_number] => 11267264 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/267264
Method of fabricating a capacitor Nov 6, 2005 Issued
Array ( [id] => 544064 [patent_doc_number] => 07163878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-16 [patent_title] => 'Ultra-shallow arsenic junction formation in silicon germanium' [patent_app_type] => utility [patent_app_number] => 11/267413 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2575 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/163/07163878.pdf [firstpage_image] =>[orig_patent_app_number] => 11267413 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/267413
Ultra-shallow arsenic junction formation in silicon germanium Nov 3, 2005 Issued
Array ( [id] => 5838226 [patent_doc_number] => 20060118884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'High-frequency switching transistor and high-frequency circuit' [patent_app_type] => utility [patent_app_number] => 11/267013 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9397 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20060118884.pdf [firstpage_image] =>[orig_patent_app_number] => 11267013 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/267013
High-frequency switching transistor and high-frequency circuit Nov 3, 2005 Issued
Array ( [id] => 5865639 [patent_doc_number] => 20060099770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Semiconductor article and method for manufacturing the semiconductor article' [patent_app_type] => utility [patent_app_number] => 11/266209 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5718 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20060099770.pdf [firstpage_image] =>[orig_patent_app_number] => 11266209 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/266209
Semiconductor article and method for manufacturing with reduced base resistance Nov 3, 2005 Issued
Array ( [id] => 5865605 [patent_doc_number] => 20060099735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Method for wafer level stack die placement' [patent_app_type] => utility [patent_app_number] => 11/263974 [patent_app_country] => US [patent_app_date] => 2005-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2692 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20060099735.pdf [firstpage_image] =>[orig_patent_app_number] => 11263974 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/263974
Method for wafer level stack die placement Nov 1, 2005 Issued
Array ( [id] => 827221 [patent_doc_number] => 07402889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/264023 [patent_app_country] => US [patent_app_date] => 2005-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 5583 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/402/07402889.pdf [firstpage_image] =>[orig_patent_app_number] => 11264023 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/264023
Semiconductor device and method for manufacturing the same Nov 1, 2005 Issued
Array ( [id] => 5922787 [patent_doc_number] => 20060240610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Structure and method for dual-gate FET with SOI substrate' [patent_app_type] => utility [patent_app_number] => 11/265464 [patent_app_country] => US [patent_app_date] => 2005-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5248 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20060240610.pdf [firstpage_image] =>[orig_patent_app_number] => 11265464 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/265464
Structure and method for dual-gate FET with SOI substrate Nov 1, 2005 Issued
Array ( [id] => 299818 [patent_doc_number] => 07538017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Method of manufacturing a thin film transistor, a thin film transistor manufactured by the method, a method of manufacturing flat panel display device, and a flat panel display device manufactured by the method' [patent_app_type] => utility [patent_app_number] => 11/263058 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3710 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/538/07538017.pdf [firstpage_image] =>[orig_patent_app_number] => 11263058 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/263058
Method of manufacturing a thin film transistor, a thin film transistor manufactured by the method, a method of manufacturing flat panel display device, and a flat panel display device manufactured by the method Oct 30, 2005 Issued
Array ( [id] => 5034822 [patent_doc_number] => 20070099361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Method for forming a semiconductor structure and structure thereof' [patent_app_type] => utility [patent_app_number] => 11/263119 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5052 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20070099361.pdf [firstpage_image] =>[orig_patent_app_number] => 11263119 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/263119
Method for forming a semiconductor structure and structure thereof Oct 30, 2005 Issued
Array ( [id] => 5034891 [patent_doc_number] => 20070099430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Method for manufacturing a semiconductor component' [patent_app_type] => utility [patent_app_number] => 11/264194 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20070099430.pdf [firstpage_image] =>[orig_patent_app_number] => 11264194 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/264194
Method for manufacturing a semiconductor component Oct 30, 2005 Issued
Array ( [id] => 285468 [patent_doc_number] => 07550395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-23 [patent_title] => 'Control of photoelectrochemical (PEC) etching by modification of the local electrochemical potential of the semiconductor structure relative to the electrolyte' [patent_app_type] => utility [patent_app_number] => 11/263314 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4713 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/550/07550395.pdf [firstpage_image] =>[orig_patent_app_number] => 11263314 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/263314
Control of photoelectrochemical (PEC) etching by modification of the local electrochemical potential of the semiconductor structure relative to the electrolyte Oct 30, 2005 Issued
Array ( [id] => 4629762 [patent_doc_number] => 08008659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-30 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/261753 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 45 [patent_no_of_words] => 24488 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/008/08008659.pdf [firstpage_image] =>[orig_patent_app_number] => 11261753 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/261753
Semiconductor integrated circuit device Oct 30, 2005 Issued
Array ( [id] => 5828244 [patent_doc_number] => 20060063279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Method of fabricating memory and memory' [patent_app_type] => utility [patent_app_number] => 11/260243 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9342 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20060063279.pdf [firstpage_image] =>[orig_patent_app_number] => 11260243 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260243
Method of fabricating memory and memory Oct 27, 2005 Issued
Array ( [id] => 5814144 [patent_doc_number] => 20060084189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'CHARACTERIZING THE INTEGRITY OF INTERCONNECTS' [patent_app_type] => utility [patent_app_number] => 11/163493 [patent_app_country] => US [patent_app_date] => 2005-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5073 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20060084189.pdf [firstpage_image] =>[orig_patent_app_number] => 11163493 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/163493
Characterizing the integrity of interconnects Oct 19, 2005 Issued
Array ( [id] => 872189 [patent_doc_number] => 07361602 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-22 [patent_title] => 'CMP process' [patent_app_type] => utility [patent_app_number] => 11/252933 [patent_app_country] => US [patent_app_date] => 2005-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1937 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/361/07361602.pdf [firstpage_image] =>[orig_patent_app_number] => 11252933 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/252933
CMP process Oct 17, 2005 Issued
Array ( [id] => 4789437 [patent_doc_number] => 20080290410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'Mosfet With Isolation Structure and Fabrication Method Thereof' [patent_app_type] => utility [patent_app_number] => 11/913044 [patent_app_country] => US [patent_app_date] => 2005-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4696 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20080290410.pdf [firstpage_image] =>[orig_patent_app_number] => 11913044 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/913044
MOSFET with isolation structure and fabrication method thereof Oct 13, 2005 Issued
Array ( [id] => 4997595 [patent_doc_number] => 20070040229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Self-assembly microstructure with polymide thin-film elastic joint' [patent_app_type] => utility [patent_app_number] => 11/248245 [patent_app_country] => US [patent_app_date] => 2005-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1782 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20070040229.pdf [firstpage_image] =>[orig_patent_app_number] => 11248245 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/248245
Self-assembly microstructure with polyimide thin-film elastic joint Oct 12, 2005 Issued
Array ( [id] => 401153 [patent_doc_number] => 07291517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-06 [patent_title] => 'Method for removing resin mask layer and method for manufacturing solder bumped substrate' [patent_app_type] => utility [patent_app_number] => 11/248183 [patent_app_country] => US [patent_app_date] => 2005-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 5449 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/291/07291517.pdf [firstpage_image] =>[orig_patent_app_number] => 11248183 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/248183
Method for removing resin mask layer and method for manufacturing solder bumped substrate Oct 12, 2005 Issued
Array ( [id] => 224899 [patent_doc_number] => 07605082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-20 [patent_title] => 'Capping before barrier-removal IC fabrication method' [patent_app_type] => utility [patent_app_number] => 11/251353 [patent_app_country] => US [patent_app_date] => 2005-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9364 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/605/07605082.pdf [firstpage_image] =>[orig_patent_app_number] => 11251353 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/251353
Capping before barrier-removal IC fabrication method Oct 12, 2005 Issued
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