Eric E. Silverman

Array ( [id] => 334191 [patent_doc_number] => 07507602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/138418 [patent_app_country] => US [patent_app_date] => 2005-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 52 [patent_no_of_words] => 11778 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/507/07507602.pdf [firstpage_image] =>[orig_patent_app_number] => 11138418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7107278 [patent_doc_number] => 20050205012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Transfer chamber for cluster system' [patent_app_type] => utility [patent_app_number] => 11/135727 [patent_app_country] => US [patent_app_date] => 2005-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2800 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20050205012.pdf [firstpage_image] =>[orig_patent_app_number] => 11135727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 535732 [patent_doc_number] => 07180144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Corner compensation method for fabricating MEMS and structure thereof' [patent_app_type] => utility [patent_app_number] => 11/129145 [patent_app_country] => US [patent_app_date] => 2005-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 3107 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180144.pdf [firstpage_image] =>[orig_patent_app_number] => 11129145 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 623510 [patent_doc_number] => 07138282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Correcting device, exposure apparatus, device production method, and device produced by the device production method' [patent_app_type] => utility [patent_app_number] => 11/125082 [patent_app_country] => US [patent_app_date] => 2005-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 8877 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/138/07138282.pdf [firstpage_image] =>[orig_patent_app_number] => 11125082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 425110 [patent_doc_number] => 07271092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-18 [patent_title] => 'Boron incorporated diffusion barrier material' [patent_app_type] => utility [patent_app_number] => 11/119370 [patent_app_country] => US [patent_app_date] => 2005-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3958 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/271/07271092.pdf [firstpage_image] =>[orig_patent_app_number] => 11119370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5832128 [patent_doc_number] => 20060243958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Microelectronic package interconnect and method of fabrication thereof' [patent_app_type] => utility [patent_app_number] => 11/116537 [patent_app_country] => US [patent_app_date] => 2005-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3051 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20060243958.pdf [firstpage_image] =>[orig_patent_app_number] => 11116537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 404609 [patent_doc_number] => 07288438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Solder deposition on wafer backside for thin-die thermal interface material' [patent_app_type] => utility [patent_app_number] => 11/116554 [patent_app_country] => US [patent_app_date] => 2005-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4936 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288438.pdf [firstpage_image] =>[orig_patent_app_number] => 11116554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7048409 [patent_doc_number] => 20050184296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'System and method for fabricating diodes' [patent_app_type] => utility [patent_app_number] => 11/111602 [patent_app_country] => US [patent_app_date] => 2005-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4258 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20050184296.pdf [firstpage_image] =>[orig_patent_app_number] => 11111602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5903070 [patent_doc_number] => 20060046207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Exposure method' [patent_app_type] => utility [patent_app_number] => 11/112454 [patent_app_country] => US [patent_app_date] => 2005-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1663 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20060046207.pdf [firstpage_image] =>[orig_patent_app_number] => 11112454 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5851241 [patent_doc_number] => 20060234432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'SOI bottom pre-doping merged e-SiGe for poly height reduction' [patent_app_type] => utility [patent_app_number] => 11/107843 [patent_app_country] => US [patent_app_date] => 2005-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 2516 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20060234432.pdf [firstpage_image] =>[orig_patent_app_number] => 11107843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7518800 [patent_doc_number] => 07972901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Chip package sealing method' [patent_app_type] => utility [patent_app_number] => 11/105635 [patent_app_country] => US [patent_app_date] => 2005-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 33 [patent_no_of_words] => 4006 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/972/07972901.pdf [firstpage_image] =>[orig_patent_app_number] => 11105635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 889142 [patent_doc_number] => 07348654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-25 [patent_title] => 'Capacitor and inductor scheme with e-fuse application' [patent_app_type] => utility [patent_app_number] => 11/106089 [patent_app_country] => US [patent_app_date] => 2005-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 6424 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/348/07348654.pdf [firstpage_image] =>[orig_patent_app_number] => 11106089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7045711 [patent_doc_number] => 20050250306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Method for manufacturing a semiconductor substrate and method for manufacturing an electro-optical device' [patent_app_type] => utility [patent_app_number] => 11/102903 [patent_app_country] => US [patent_app_date] => 2005-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4912 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20050250306.pdf [firstpage_image] =>[orig_patent_app_number] => 11102903 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5705371 [patent_doc_number] => 20060194419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Crystalline-si-layer-bearing substrate and its production method, and crystalline si device' [patent_app_type] => utility [patent_app_number] => 10/552513 [patent_app_country] => US [patent_app_date] => 2005-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7587 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20060194419.pdf [firstpage_image] =>[orig_patent_app_number] => 10552513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5751032 [patent_doc_number] => 20060220181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Controllable varactor within dummy substrate pattern' [patent_app_type] => utility [patent_app_number] => 11/097743 [patent_app_country] => US [patent_app_date] => 2005-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2307 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20060220181.pdf [firstpage_image] =>[orig_patent_app_number] => 11097743 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 141794 [patent_doc_number] => 07687409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Atomic layer deposited titanium silicon oxide films' [patent_app_type] => utility [patent_app_number] => 11/093104 [patent_app_country] => US [patent_app_date] => 2005-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 10867 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/687/07687409.pdf [firstpage_image] =>[orig_patent_app_number] => 11093104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5707545 [patent_doc_number] => 20060048889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Method for connecting a chip and a substrate' [patent_app_type] => utility [patent_app_number] => 11/088514 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3768 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20060048889.pdf [firstpage_image] =>[orig_patent_app_number] => 11088514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5141918 [patent_doc_number] => 20070004134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Vertically integrated flash EPROM for greater density and lower cost' [patent_app_type] => utility [patent_app_number] => 11/083683 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 17766 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20070004134.pdf [firstpage_image] =>[orig_patent_app_number] => 11083683 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5785524 [patent_doc_number] => 20060205113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Radio frequency identification (RFID) tag lamination process' [patent_app_type] => utility [patent_app_number] => 11/079143 [patent_app_country] => US [patent_app_date] => 2005-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1985 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20060205113.pdf [firstpage_image] =>[orig_patent_app_number] => 11079143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7136852 [patent_doc_number] => 20050181541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Method of producing a COF flexible printed wiring board' [patent_app_type] => utility [patent_app_number] => 11/078293 [patent_app_country] => US [patent_app_date] => 2005-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9055 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20050181541.pdf [firstpage_image] =>[orig_patent_app_number] => 11078293 [rel_patent_id] =>[rel_patent_doc_number] =>)