Search

Eric E. Silverman

Examiner (ID: 15411)

Most Active Art Unit
1618
Art Unit(s)
1618, 1615
Total Applications
298
Issued Applications
111
Pending Applications
2
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7197253 [patent_doc_number] => 20050164480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Interface layer for the fabrication of electronic devices' [patent_app_type] => utility [patent_app_number] => 11/077240 [patent_app_country] => US [patent_app_date] => 2005-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5436 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20050164480.pdf [firstpage_image] =>[orig_patent_app_number] => 11077240 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/077240
Interface layer for the fabrication of electronic devices Mar 8, 2005 Issued
Array ( [id] => 5085435 [patent_doc_number] => 20070275486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'Equipment And Method For Processing Semiconductor' [patent_app_type] => utility [patent_app_number] => 10/592503 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20070275486.pdf [firstpage_image] =>[orig_patent_app_number] => 10592503 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/592503
Equipment and method for processing semiconductor Feb 23, 2005 Issued
Array ( [id] => 7236691 [patent_doc_number] => 20050140000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Method of manufacturing a semiconductor device and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/065564 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3196 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140000.pdf [firstpage_image] =>[orig_patent_app_number] => 11065564 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/065564
Electrode-type heat sink Feb 23, 2005 Issued
Array ( [id] => 484457 [patent_doc_number] => 07221038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Method of fabricating substrates and substrates obtained by this method' [patent_app_type] => utility [patent_app_number] => 11/057171 [patent_app_country] => US [patent_app_date] => 2005-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7208 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/221/07221038.pdf [firstpage_image] =>[orig_patent_app_number] => 11057171 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/057171
Method of fabricating substrates and substrates obtained by this method Feb 14, 2005 Issued
Array ( [id] => 7071905 [patent_doc_number] => 20050145171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Processing method utilizing an apparatus to be sealed against workpiece' [patent_app_type] => utility [patent_app_number] => 11/054061 [patent_app_country] => US [patent_app_date] => 2005-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5139 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20050145171.pdf [firstpage_image] =>[orig_patent_app_number] => 11054061 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/054061
Processing method utilizing an apparatus to be sealed against workpiece Feb 9, 2005 Issued
Array ( [id] => 911302 [patent_doc_number] => 07329911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-12 [patent_title] => 'Semiconductor device including memory cell and anti-fuse element' [patent_app_type] => utility [patent_app_number] => 11/052803 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6346 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/329/07329911.pdf [firstpage_image] =>[orig_patent_app_number] => 11052803 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/052803
Semiconductor device including memory cell and anti-fuse element Feb 8, 2005 Issued
Array ( [id] => 707665 [patent_doc_number] => 07060587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Method for forming macropores in a layer and products obtained thereof' [patent_app_type] => utility [patent_app_number] => 11/045954 [patent_app_country] => US [patent_app_date] => 2005-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3770 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/060/07060587.pdf [firstpage_image] =>[orig_patent_app_number] => 11045954 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/045954
Method for forming macropores in a layer and products obtained thereof Jan 27, 2005 Issued
90/007390 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING A BIPOLAR TRANSISTOR AND A VARIABLE CAPACITOR Jan 23, 2005 Pending
Array ( [id] => 6931480 [patent_doc_number] => 20050282515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Receiver circuit using nanotube-based switches and transistors' [patent_app_type] => utility [patent_app_number] => 11/033213 [patent_app_country] => US [patent_app_date] => 2005-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7199 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20050282515.pdf [firstpage_image] =>[orig_patent_app_number] => 11033213 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/033213
Receiver circuit using nanotube-based switches and transistors Jan 9, 2005 Issued
Array ( [id] => 439356 [patent_doc_number] => 07259105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-21 [patent_title] => 'Methods of fabricating gate spacers for semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/026937 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1180 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/259/07259105.pdf [firstpage_image] =>[orig_patent_app_number] => 11026937 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/026937
Methods of fabricating gate spacers for semiconductor devices Dec 29, 2004 Issued
Array ( [id] => 7066999 [patent_doc_number] => 20050242381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'Ferroelectric capacitor, process for production thereof and semiconductor device using the same' [patent_app_type] => utility [patent_app_number] => 11/024873 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4947 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20050242381.pdf [firstpage_image] =>[orig_patent_app_number] => 11024873 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024873
Ferroelectric capacitor, process for production thereof and semiconductor device using the same Dec 29, 2004 Issued
Array ( [id] => 606377 [patent_doc_number] => 07153742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-26 [patent_title] => 'Method for fabricating flash memory device' [patent_app_type] => utility [patent_app_number] => 11/024193 [patent_app_country] => US [patent_app_date] => 2004-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1793 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/153/07153742.pdf [firstpage_image] =>[orig_patent_app_number] => 11024193 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024193
Method for fabricating flash memory device Dec 28, 2004 Issued
Array ( [id] => 482540 [patent_doc_number] => 07220628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Semiconductor device and manufacturing method thereof, and gate electrode and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/022987 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 39 [patent_no_of_words] => 14560 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/220/07220628.pdf [firstpage_image] =>[orig_patent_app_number] => 11022987 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/022987
Semiconductor device and manufacturing method thereof, and gate electrode and manufacturing method thereof Dec 27, 2004 Issued
Array ( [id] => 377022 [patent_doc_number] => 07312122 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Self-aligned element isolation film structure in a flash cell and forming method thereof' [patent_app_type] => utility [patent_app_number] => 11/023277 [patent_app_country] => US [patent_app_date] => 2004-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1288 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/312/07312122.pdf [firstpage_image] =>[orig_patent_app_number] => 11023277 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/023277
Self-aligned element isolation film structure in a flash cell and forming method thereof Dec 26, 2004 Issued
Array ( [id] => 7073573 [patent_doc_number] => 20050146839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Forming thin layer structures by ablation' [patent_app_type] => utility [patent_app_number] => 11/019823 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3545 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20050146839.pdf [firstpage_image] =>[orig_patent_app_number] => 11019823 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019823
Forming thin layer structures by ablation Dec 21, 2004 Abandoned
Array ( [id] => 366563 [patent_doc_number] => 07479431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-20 [patent_title] => 'Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain' [patent_app_type] => utility [patent_app_number] => 11/014937 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2144 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/479/07479431.pdf [firstpage_image] =>[orig_patent_app_number] => 11014937 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/014937
Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain Dec 16, 2004 Issued
Array ( [id] => 5188646 [patent_doc_number] => 20070166954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Method for manufacturing thin film integrated circuit device, noncontact thin film integrated circuit device and method for manufacturing the same, and idtag and coin including the noncontact thin film integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/581674 [patent_app_country] => US [patent_app_date] => 2004-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 15016 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20070166954.pdf [firstpage_image] =>[orig_patent_app_number] => 10581674 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/581674
Method for manufacturing thin film integrated circuit device, noncontact thin film integrated circuit device and method for manufacturing the same, and idtag and coin including the noncontact thin film integrated circuit device Dec 13, 2004 Issued
Array ( [id] => 428988 [patent_doc_number] => 07268424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Semiconductor device, electronic card and pad rearrangement substrate' [patent_app_type] => utility [patent_app_number] => 11/005387 [patent_app_country] => US [patent_app_date] => 2004-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 45 [patent_no_of_words] => 7194 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/268/07268424.pdf [firstpage_image] =>[orig_patent_app_number] => 11005387 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/005387
Semiconductor device, electronic card and pad rearrangement substrate Dec 5, 2004 Issued
Array ( [id] => 334588 [patent_doc_number] => 07508000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Method of fabricating self-aligned silicon carbide semiconductor devices' [patent_app_type] => utility [patent_app_number] => 10/997057 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 60 [patent_no_of_words] => 6722 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/508/07508000.pdf [firstpage_image] =>[orig_patent_app_number] => 10997057 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997057
Method of fabricating self-aligned silicon carbide semiconductor devices Nov 23, 2004 Issued
Array ( [id] => 917030 [patent_doc_number] => 07323387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Method to make nano structure below 25 nanometer with high uniformity on large scale' [patent_app_type] => utility [patent_app_number] => 10/987743 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3711 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/323/07323387.pdf [firstpage_image] =>[orig_patent_app_number] => 10987743 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/987743
Method to make nano structure below 25 nanometer with high uniformity on large scale Nov 11, 2004 Issued
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