Search

Eric E. Silverman

Examiner (ID: 15411)

Most Active Art Unit
1618
Art Unit(s)
1618, 1615
Total Applications
298
Issued Applications
111
Pending Applications
2
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7361250 [patent_doc_number] => 20040216989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'MEMS switch having hexsil beam and method of integrating MEMS switch with a chip' [patent_app_type] => new [patent_app_number] => 10/857101 [patent_app_country] => US [patent_app_date] => 2004-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3223 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20040216989.pdf [firstpage_image] =>[orig_patent_app_number] => 10857101 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/857101
MEMS switch having hexsil beam and method of integrating MEMS switch with a chip May 27, 2004 Issued
Array ( [id] => 394317 [patent_doc_number] => 07298016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Electromechanical memory array using nanotube ribbons and method for making same' [patent_app_type] => utility [patent_app_number] => 10/852880 [patent_app_country] => US [patent_app_date] => 2004-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 6424 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/298/07298016.pdf [firstpage_image] =>[orig_patent_app_number] => 10852880 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/852880
Electromechanical memory array using nanotube ribbons and method for making same May 24, 2004 Issued
Array ( [id] => 5038191 [patent_doc_number] => 20070090473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Microelectromechanical component and method for the production thereof' [patent_app_type] => utility [patent_app_number] => 10/558114 [patent_app_country] => US [patent_app_date] => 2004-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2895 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20070090473.pdf [firstpage_image] =>[orig_patent_app_number] => 10558114 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/558114
Microelectromechanical component and method for the production thereof May 23, 2004 Issued
10/709654 METHOD FOR APPLYING A LAYER TO A HYDROPHOBIC SURFACE May 19, 2004 Abandoned
Array ( [id] => 419114 [patent_doc_number] => 07276789 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-02 [patent_title] => 'Microelectromechanical systems using thermocompression bonding' [patent_app_type] => utility [patent_app_number] => 10/851751 [patent_app_country] => US [patent_app_date] => 2004-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 9846 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/276/07276789.pdf [firstpage_image] =>[orig_patent_app_number] => 10851751 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/851751
Microelectromechanical systems using thermocompression bonding May 19, 2004 Issued
Array ( [id] => 710606 [patent_doc_number] => 07056758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Electromechanical memory array using nanotube ribbons and method for making same' [patent_app_type] => utility [patent_app_number] => 10/850100 [patent_app_country] => US [patent_app_date] => 2004-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 6423 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/056/07056758.pdf [firstpage_image] =>[orig_patent_app_number] => 10850100 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/850100
Electromechanical memory array using nanotube ribbons and method for making same May 19, 2004 Issued
Array ( [id] => 467115 [patent_doc_number] => 07235415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Film pattern formation method, device and method for manufacturing the same, electro-optical device, electronic device, and method for manufacturing active matrix substrate' [patent_app_type] => utility [patent_app_number] => 10/848604 [patent_app_country] => US [patent_app_date] => 2004-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 32 [patent_no_of_words] => 19467 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/235/07235415.pdf [firstpage_image] =>[orig_patent_app_number] => 10848604 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/848604
Film pattern formation method, device and method for manufacturing the same, electro-optical device, electronic device, and method for manufacturing active matrix substrate May 18, 2004 Issued
Array ( [id] => 847114 [patent_doc_number] => 07384814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-10 [patent_title] => 'Field effect transistor including an organic semiconductor and a dielectric layer having a substantially same pattern' [patent_app_type] => utility [patent_app_number] => 10/557623 [patent_app_country] => US [patent_app_date] => 2004-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5714 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/384/07384814.pdf [firstpage_image] =>[orig_patent_app_number] => 10557623 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/557623
Field effect transistor including an organic semiconductor and a dielectric layer having a substantially same pattern May 12, 2004 Issued
Array ( [id] => 7230232 [patent_doc_number] => 20050255699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'METHOD FOR CONTROLLING VOIDING AND BRIDGING IN SILICIDE FORMATION' [patent_app_type] => utility [patent_app_number] => 10/709534 [patent_app_country] => US [patent_app_date] => 2004-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2295 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20050255699.pdf [firstpage_image] =>[orig_patent_app_number] => 10709534 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709534
Method for controlling voiding and bridging in silicide formation May 11, 2004 Issued
Array ( [id] => 7429085 [patent_doc_number] => 20040209421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Semiconductor processing methods of forming integrated circuitry' [patent_app_type] => new [patent_app_number] => 10/844714 [patent_app_country] => US [patent_app_date] => 2004-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2788 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20040209421.pdf [firstpage_image] =>[orig_patent_app_number] => 10844714 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/844714
Semiconductor processing methods of forming integrated circuitry May 11, 2004 Issued
Array ( [id] => 390267 [patent_doc_number] => 07300863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Circuit chip connector and method of connecting a circuit chip' [patent_app_type] => utility [patent_app_number] => 10/843174 [patent_app_country] => US [patent_app_date] => 2004-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 5457 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/300/07300863.pdf [firstpage_image] =>[orig_patent_app_number] => 10843174 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/843174
Circuit chip connector and method of connecting a circuit chip May 10, 2004 Issued
Array ( [id] => 662573 [patent_doc_number] => 07101722 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-05 [patent_title] => 'In-line voltage contrast determination of tunnel oxide weakness in integrated circuit technology development' [patent_app_type] => utility [patent_app_number] => 10/839444 [patent_app_country] => US [patent_app_date] => 2004-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3134 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/101/07101722.pdf [firstpage_image] =>[orig_patent_app_number] => 10839444 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/839444
In-line voltage contrast determination of tunnel oxide weakness in integrated circuit technology development May 3, 2004 Issued
Array ( [id] => 708586 [patent_doc_number] => 07061021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'System and method for fabricating diodes' [patent_app_type] => utility [patent_app_number] => 10/837862 [patent_app_country] => US [patent_app_date] => 2004-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4187 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/061/07061021.pdf [firstpage_image] =>[orig_patent_app_number] => 10837862 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/837862
System and method for fabricating diodes May 2, 2004 Issued
Array ( [id] => 7462429 [patent_doc_number] => 20040198001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Method of generating multiple oxides by plasma nitridation on oxide' [patent_app_type] => new [patent_app_number] => 10/831874 [patent_app_country] => US [patent_app_date] => 2004-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6892 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20040198001.pdf [firstpage_image] =>[orig_patent_app_number] => 10831874 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/831874
Method of generating multiple oxides by plasma nitridation on oxide Apr 25, 2004 Issued
Array ( [id] => 243214 [patent_doc_number] => 07588948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Test structure for electrically verifying the depths of trench-etching in an SOI wafer, and associated working methods' [patent_app_type] => utility [patent_app_number] => 10/552984 [patent_app_country] => US [patent_app_date] => 2004-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3312 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/588/07588948.pdf [firstpage_image] =>[orig_patent_app_number] => 10552984 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/552984
Test structure for electrically verifying the depths of trench-etching in an SOI wafer, and associated working methods Apr 18, 2004 Issued
Array ( [id] => 5785642 [patent_doc_number] => 20060205171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Chip resistor and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 10/553044 [patent_app_country] => US [patent_app_date] => 2004-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4622 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20060205171.pdf [firstpage_image] =>[orig_patent_app_number] => 10553044 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/553044
Chip resistor and method for manufacturing same Apr 15, 2004 Issued
Array ( [id] => 7692004 [patent_doc_number] => 20070232029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Method of Three-Dimensional Microfabrication and High-Density Three-Dimensional Fine Structure' [patent_app_type] => utility [patent_app_number] => 11/578034 [patent_app_country] => US [patent_app_date] => 2004-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3991 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20070232029.pdf [firstpage_image] =>[orig_patent_app_number] => 11578034 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/578034
Method of three-dimensional microfabrication and high-density three-dimentional fine structure Apr 12, 2004 Issued
Array ( [id] => 5760323 [patent_doc_number] => 20060211268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Method and apparatus for processing organosiloxane film' [patent_app_type] => utility [patent_app_number] => 10/552993 [patent_app_country] => US [patent_app_date] => 2004-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5911 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20060211268.pdf [firstpage_image] =>[orig_patent_app_number] => 10552993 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/552993
Method and apparatus for processing organosiloxane film Apr 12, 2004 Issued
Array ( [id] => 7601484 [patent_doc_number] => 07385220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-10 [patent_title] => 'Fiber having dielectric polymeric layer on electrically conductive surface' [patent_app_type] => utility [patent_app_number] => 10/822510 [patent_app_country] => US [patent_app_date] => 2004-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 18139 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/385/07385220.pdf [firstpage_image] =>[orig_patent_app_number] => 10822510 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/822510
Fiber having dielectric polymeric layer on electrically conductive surface Apr 11, 2004 Issued
Array ( [id] => 938434 [patent_doc_number] => 06972263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-06 [patent_title] => 'Fabricating a tapered hole incorporating a resinous silicon containing film' [patent_app_type] => utility [patent_app_number] => 10/819964 [patent_app_country] => US [patent_app_date] => 2004-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 33 [patent_no_of_words] => 5861 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972263.pdf [firstpage_image] =>[orig_patent_app_number] => 10819964 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/819964
Fabricating a tapered hole incorporating a resinous silicon containing film Apr 7, 2004 Issued
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