Search

Eric E. Silverman

Examiner (ID: 15411)

Most Active Art Unit
1618
Art Unit(s)
1618, 1615
Total Applications
298
Issued Applications
111
Pending Applications
2
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7419022 [patent_doc_number] => 20040000333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Monolithically integrated solid-state sige thermoelectric energy converter for high speed and low power circuits' [patent_app_type] => new [patent_app_number] => 10/459974 [patent_app_country] => US [patent_app_date] => 2003-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5006 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20040000333.pdf [firstpage_image] =>[orig_patent_app_number] => 10459974 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/459974
Monolithically integrated solid-state sige thermoelectric energy converter for high speed and low power circuits Jun 11, 2003 Issued
Array ( [id] => 7398876 [patent_doc_number] => 20040018694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Methods for forming silicon dioxide layers on substrates using atomic layer deposition' [patent_app_type] => new [patent_app_number] => 10/459943 [patent_app_country] => US [patent_app_date] => 2003-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6557 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20040018694.pdf [firstpage_image] =>[orig_patent_app_number] => 10459943 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/459943
Methods for forming silicon dioxide layers on substrates using atomic layer deposition Jun 11, 2003 Issued
Array ( [id] => 6723406 [patent_doc_number] => 20030205718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Light-emitting semiconductor device using group III nitride compound' [patent_app_type] => new [patent_app_number] => 10/456509 [patent_app_country] => US [patent_app_date] => 2003-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3242 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20030205718.pdf [firstpage_image] =>[orig_patent_app_number] => 10456509 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/456509
Light-emitting semiconductor device using group III nitride compound Jun 8, 2003 Abandoned
Array ( [id] => 6723486 [patent_doc_number] => 20030205798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Semiconductor die package including carrier with mask' [patent_app_type] => new [patent_app_number] => 10/455511 [patent_app_country] => US [patent_app_date] => 2003-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5206 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20030205798.pdf [firstpage_image] =>[orig_patent_app_number] => 10455511 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/455511
Semiconductor die package including carrier with mask and semiconductor die Jun 3, 2003 Issued
Array ( [id] => 390233 [patent_doc_number] => 07300829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Low temperature process for TFT fabrication' [patent_app_type] => utility [patent_app_number] => 10/453333 [patent_app_country] => US [patent_app_date] => 2003-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 9122 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/300/07300829.pdf [firstpage_image] =>[orig_patent_app_number] => 10453333 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/453333
Low temperature process for TFT fabrication Jun 1, 2003 Issued
Array ( [id] => 1102651 [patent_doc_number] => 06815754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Spacer patterned, high dielectric constant capacitor' [patent_app_type] => B2 [patent_app_number] => 10/441733 [patent_app_country] => US [patent_app_date] => 2003-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 4229 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815754.pdf [firstpage_image] =>[orig_patent_app_number] => 10441733 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/441733
Spacer patterned, high dielectric constant capacitor May 19, 2003 Issued
Array ( [id] => 5738568 [patent_doc_number] => 20060008959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Layer arrangement and memory arrangement' [patent_app_type] => utility [patent_app_number] => 10/514168 [patent_app_country] => US [patent_app_date] => 2003-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10667 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20060008959.pdf [firstpage_image] =>[orig_patent_app_number] => 10514168 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/514168
Method for fabricating a layer arrangement, layer arrangement and memory arrangement May 14, 2003 Issued
Array ( [id] => 931368 [patent_doc_number] => 06979872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Modules integrating MEMS devices with pre-processed electronic circuitry, and methods for fabricating such modules' [patent_app_type] => utility [patent_app_number] => 10/438512 [patent_app_country] => US [patent_app_date] => 2003-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3517 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/979/06979872.pdf [firstpage_image] =>[orig_patent_app_number] => 10438512 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/438512
Modules integrating MEMS devices with pre-processed electronic circuitry, and methods for fabricating such modules May 12, 2003 Issued
Array ( [id] => 1002317 [patent_doc_number] => 06908771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'Method for fabricating dc SQUID using high-Tc superconducting intrinsic Josephson junctions' [patent_app_type] => utility [patent_app_number] => 10/434224 [patent_app_country] => US [patent_app_date] => 2003-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2874 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/908/06908771.pdf [firstpage_image] =>[orig_patent_app_number] => 10434224 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/434224
Method for fabricating dc SQUID using high-Tc superconducting intrinsic Josephson junctions May 8, 2003 Issued
Array ( [id] => 7317380 [patent_doc_number] => 20040224262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Direct alignment scheme between multiple lithography layers' [patent_app_type] => new [patent_app_number] => 10/435495 [patent_app_country] => US [patent_app_date] => 2003-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2826 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20040224262.pdf [firstpage_image] =>[orig_patent_app_number] => 10435495 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435495
Direct alignment scheme between multiple lithography layers May 7, 2003 Issued
Array ( [id] => 6809222 [patent_doc_number] => 20030199161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MAKING THE SAME' [patent_app_type] => new [patent_app_number] => 10/430402 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6377 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 375 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20030199161.pdf [firstpage_image] =>[orig_patent_app_number] => 10430402 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/430402
Semiconductor integrated circuit device and method for making the same May 6, 2003 Issued
Array ( [id] => 6725175 [patent_doc_number] => 20030207487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Single crystal, dual wafer, tunneling sensor and a method of making same' [patent_app_type] => new [patent_app_number] => 10/429988 [patent_app_country] => US [patent_app_date] => 2003-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7743 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20030207487.pdf [firstpage_image] =>[orig_patent_app_number] => 10429988 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/429988
Single crystal, dual wafer, tunneling sensor and a method of making same May 5, 2003 Issued
Array ( [id] => 563883 [patent_doc_number] => 07157781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Enhancement of membrane characteristics in semiconductor device with membrane' [patent_app_type] => utility [patent_app_number] => 10/425663 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 5299 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/157/07157781.pdf [firstpage_image] =>[orig_patent_app_number] => 10425663 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/425663
Enhancement of membrane characteristics in semiconductor device with membrane Apr 29, 2003 Issued
Array ( [id] => 7617136 [patent_doc_number] => 06946304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-20 [patent_title] => 'Apparatus for and method of manufacturing a semiconductor device, and cleaning method for use in the apparatus for manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/424906 [patent_app_country] => US [patent_app_date] => 2003-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9474 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/946/06946304.pdf [firstpage_image] =>[orig_patent_app_number] => 10424906 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/424906
Apparatus for and method of manufacturing a semiconductor device, and cleaning method for use in the apparatus for manufacturing a semiconductor device Apr 28, 2003 Issued
Array ( [id] => 627007 [patent_doc_number] => 07135390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Method of fabricating a semiconductor device incorporating crystallizing by laser irradiation' [patent_app_type] => utility [patent_app_number] => 10/424874 [patent_app_country] => US [patent_app_date] => 2003-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 9552 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/135/07135390.pdf [firstpage_image] =>[orig_patent_app_number] => 10424874 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/424874
Method of fabricating a semiconductor device incorporating crystallizing by laser irradiation Apr 28, 2003 Issued
Array ( [id] => 435863 [patent_doc_number] => 07262119 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-08-28 [patent_title] => 'Method for incorporating germanium into a semiconductor wafer' [patent_app_type] => utility [patent_app_number] => 10/423184 [patent_app_country] => US [patent_app_date] => 2003-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 26 [patent_no_of_words] => 3368 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/262/07262119.pdf [firstpage_image] =>[orig_patent_app_number] => 10423184 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/423184
Method for incorporating germanium into a semiconductor wafer Apr 24, 2003 Issued
Array ( [id] => 797943 [patent_doc_number] => 07427529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-23 [patent_title] => 'Deposition of permanent polymer structures for OLED fabrication' [patent_app_type] => utility [patent_app_number] => 10/422212 [patent_app_country] => US [patent_app_date] => 2003-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 15639 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/427/07427529.pdf [firstpage_image] =>[orig_patent_app_number] => 10422212 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/422212
Deposition of permanent polymer structures for OLED fabrication Apr 22, 2003 Issued
Array ( [id] => 404952 [patent_doc_number] => 07288785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Substrate and method for measuring the electro-physiological properties of cell membranes' [patent_app_type] => utility [patent_app_number] => 10/417327 [patent_app_country] => US [patent_app_date] => 2003-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 9683 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288785.pdf [firstpage_image] =>[orig_patent_app_number] => 10417327 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/417327
Substrate and method for measuring the electro-physiological properties of cell membranes Apr 16, 2003 Issued
Array ( [id] => 349230 [patent_doc_number] => 07495348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Process for producing copy protection for an electronic circuit' [patent_app_type] => utility [patent_app_number] => 10/511558 [patent_app_country] => US [patent_app_date] => 2003-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 5822 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/495/07495348.pdf [firstpage_image] =>[orig_patent_app_number] => 10511558 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/511558
Process for producing copy protection for an electronic circuit Apr 14, 2003 Issued
Array ( [id] => 539563 [patent_doc_number] => 07176514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Method and configuration for reinforcement of a dielectric layer at defects by self-aligning and self-limiting electrochemical conversion of a substrate material' [patent_app_type] => utility [patent_app_number] => 10/413812 [patent_app_country] => US [patent_app_date] => 2003-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5129 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/176/07176514.pdf [firstpage_image] =>[orig_patent_app_number] => 10413812 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/413812
Method and configuration for reinforcement of a dielectric layer at defects by self-aligning and self-limiting electrochemical conversion of a substrate material Apr 14, 2003 Issued
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