
Eric E. Silverman
Examiner (ID: 15411)
| Most Active Art Unit | 1618 |
| Art Unit(s) | 1618, 1615 |
| Total Applications | 298 |
| Issued Applications | 111 |
| Pending Applications | 2 |
| Abandoned Applications | 185 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1101567
[patent_doc_number] => 06815250
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-09
[patent_title] => 'Method for manufacturing infrared detector using diffusion of hydrogen plasma'
[patent_app_type] => B1
[patent_app_number] => 10/342864
[patent_app_country] => US
[patent_app_date] => 2003-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2872
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/815/06815250.pdf
[firstpage_image] =>[orig_patent_app_number] => 10342864
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/342864 | Method for manufacturing infrared detector using diffusion of hydrogen plasma | Jan 14, 2003 | Issued |
Array
(
[id] => 7365079
[patent_doc_number] => 20040092052
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-13
[patent_title] => 'Film deposition method for stess balance'
[patent_app_type] => new
[patent_app_number] => 10/341803
[patent_app_country] => US
[patent_app_date] => 2003-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1923
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0092/20040092052.pdf
[firstpage_image] =>[orig_patent_app_number] => 10341803
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/341803 | Deposition method for balancing film stress | Jan 13, 2003 | Issued |
Array
(
[id] => 6711225
[patent_doc_number] => 20030170974
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-11
[patent_title] => 'Method of fabricating a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/339454
[patent_app_country] => US
[patent_app_date] => 2003-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5282
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0170/20030170974.pdf
[firstpage_image] =>[orig_patent_app_number] => 10339454
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/339454 | Method of fabricating a semiconductor device | Jan 9, 2003 | Issued |
Array
(
[id] => 7427490
[patent_doc_number] => 20040007748
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-15
[patent_title] => 'Semiconductor device, and method of fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/337724
[patent_app_country] => US
[patent_app_date] => 2003-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 29244
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0007/20040007748.pdf
[firstpage_image] =>[orig_patent_app_number] => 10337724
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/337724 | Method of fabricating a semiconductor device | Jan 7, 2003 | Issued |
Array
(
[id] => 6801343
[patent_doc_number] => 20030096508
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-22
[patent_title] => 'Method of depositing dielectric'
[patent_app_type] => new
[patent_app_number] => 10/336923
[patent_app_country] => US
[patent_app_date] => 2003-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1149
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 19
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0096/20030096508.pdf
[firstpage_image] =>[orig_patent_app_number] => 10336923
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/336923 | Method of depositing dielectric | Jan 5, 2003 | Issued |
Array
(
[id] => 534675
[patent_doc_number] => 07172979
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-06
[patent_title] => 'Substrate processing apparatus and method'
[patent_app_type] => utility
[patent_app_number] => 10/481424
[patent_app_country] => US
[patent_app_date] => 2002-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 32
[patent_no_of_words] => 18016
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/172/07172979.pdf
[firstpage_image] =>[orig_patent_app_number] => 10481424
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/481424 | Substrate processing apparatus and method | Dec 25, 2002 | Issued |
Array
(
[id] => 6851622
[patent_doc_number] => 20030143825
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-31
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/326113
[patent_app_country] => US
[patent_app_date] => 2002-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7067
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0143/20030143825.pdf
[firstpage_image] =>[orig_patent_app_number] => 10326113
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/326113 | Semiconductor device and method of manufacturing the same | Dec 22, 2002 | Issued |
Array
(
[id] => 6805077
[patent_doc_number] => 20030232471
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-18
[patent_title] => 'Semiconductor device and method of fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/326143
[patent_app_country] => US
[patent_app_date] => 2002-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 3109
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0232/20030232471.pdf
[firstpage_image] =>[orig_patent_app_number] => 10326143
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/326143 | Semiconductor device and method of fabricating the same | Dec 22, 2002 | Abandoned |
Array
(
[id] => 7456866
[patent_doc_number] => 20040119125
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-24
[patent_title] => 'Semiconductor structure and method of manufacture'
[patent_app_type] => new
[patent_app_number] => 10/328923
[patent_app_country] => US
[patent_app_date] => 2002-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3935
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0119/20040119125.pdf
[firstpage_image] =>[orig_patent_app_number] => 10328923
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/328923 | Method for forming a semiconductor structure through epitaxial growth | Dec 22, 2002 | Issued |
Array
(
[id] => 448420
[patent_doc_number] => 07250317
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-31
[patent_title] => 'Method of fabricating optical waveguide reflectors'
[patent_app_type] => utility
[patent_app_number] => 10/499579
[patent_app_country] => US
[patent_app_date] => 2002-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 3458
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/250/07250317.pdf
[firstpage_image] =>[orig_patent_app_number] => 10499579
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/499579 | Method of fabricating optical waveguide reflectors | Dec 19, 2002 | Issued |
Array
(
[id] => 5913009
[patent_doc_number] => 20060128071
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'Integrated antifuse structure for finfet and cmos devices'
[patent_app_type] => utility
[patent_app_number] => 10/539333
[patent_app_country] => US
[patent_app_date] => 2002-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2743
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0128/20060128071.pdf
[firstpage_image] =>[orig_patent_app_number] => 10539333
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/539333 | Integrated antifuse structure for FINFET and CMOS devices | Dec 19, 2002 | Issued |
Array
(
[id] => 1073689
[patent_doc_number] => 06838354
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-04
[patent_title] => 'Method for forming a passivation layer for air gap formation'
[patent_app_type] => utility
[patent_app_number] => 10/327403
[patent_app_country] => US
[patent_app_date] => 2002-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 9202
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/838/06838354.pdf
[firstpage_image] =>[orig_patent_app_number] => 10327403
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/327403 | Method for forming a passivation layer for air gap formation | Dec 19, 2002 | Issued |
Array
(
[id] => 1043662
[patent_doc_number] => 06867095
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-15
[patent_title] => 'Method for the fabrication of a semiconductor device utilizing simultaneous formation of contact plugs'
[patent_app_type] => utility
[patent_app_number] => 10/324304
[patent_app_country] => US
[patent_app_date] => 2002-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1857
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/867/06867095.pdf
[firstpage_image] =>[orig_patent_app_number] => 10324304
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/324304 | Method for the fabrication of a semiconductor device utilizing simultaneous formation of contact plugs | Dec 19, 2002 | Issued |
Array
(
[id] => 1180168
[patent_doc_number] => 06740604
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-05-25
[patent_title] => 'Method of separating two layers of material from one another'
[patent_app_type] => B2
[patent_app_number] => 10/324848
[patent_app_country] => US
[patent_app_date] => 2002-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4983
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/740/06740604.pdf
[firstpage_image] =>[orig_patent_app_number] => 10324848
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/324848 | Method of separating two layers of material from one another | Dec 19, 2002 | Issued |
Array
(
[id] => 7471625
[patent_doc_number] => 20040121575
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-24
[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH BURIED CONDUCTIVE LINES'
[patent_app_type] => new
[patent_app_number] => 10/322654
[patent_app_country] => US
[patent_app_date] => 2002-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2089
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0121/20040121575.pdf
[firstpage_image] =>[orig_patent_app_number] => 10322654
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/322654 | Method of manufacturing semiconductor device with buried conductive lines | Dec 18, 2002 | Issued |
Array
(
[id] => 1063728
[patent_doc_number] => 06849928
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-01
[patent_title] => 'Dual silicon-on-insulator device wafer die'
[patent_app_type] => utility
[patent_app_number] => 10/327309
[patent_app_country] => US
[patent_app_date] => 2002-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 1661
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/849/06849928.pdf
[firstpage_image] =>[orig_patent_app_number] => 10327309
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/327309 | Dual silicon-on-insulator device wafer die | Dec 18, 2002 | Issued |
Array
(
[id] => 576915
[patent_doc_number] => 07456105
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-11-25
[patent_title] => 'CMP metal polishing slurry and process with reduced solids concentration'
[patent_app_type] => utility
[patent_app_number] => 10/321973
[patent_app_country] => US
[patent_app_date] => 2002-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 17
[patent_no_of_words] => 5566
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/456/07456105.pdf
[firstpage_image] =>[orig_patent_app_number] => 10321973
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/321973 | CMP metal polishing slurry and process with reduced solids concentration | Dec 16, 2002 | Issued |
Array
(
[id] => 972097
[patent_doc_number] => 06936482
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-30
[patent_title] => 'Method of fabricating substrates and substrates obtained by this method'
[patent_app_type] => utility
[patent_app_number] => 10/320063
[patent_app_country] => US
[patent_app_date] => 2002-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 7028
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/936/06936482.pdf
[firstpage_image] =>[orig_patent_app_number] => 10320063
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/320063 | Method of fabricating substrates and substrates obtained by this method | Dec 15, 2002 | Issued |
Array
(
[id] => 5631656
[patent_doc_number] => 20060148126
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-06
[patent_title] => 'Method for manufacturing printed wiring board'
[patent_app_type] => utility
[patent_app_number] => 10/537994
[patent_app_country] => US
[patent_app_date] => 2002-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2143
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0148/20060148126.pdf
[firstpage_image] =>[orig_patent_app_number] => 10537994
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/537994 | Method for manufacturing printed wiring board | Dec 11, 2002 | Issued |
Array
(
[id] => 1080541
[patent_doc_number] => 06835675
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-12-28
[patent_title] => 'Laser-irradiation method and laser-irradiation device'
[patent_app_type] => B2
[patent_app_number] => 10/316605
[patent_app_country] => US
[patent_app_date] => 2002-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 27
[patent_no_of_words] => 13576
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/835/06835675.pdf
[firstpage_image] =>[orig_patent_app_number] => 10316605
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/316605 | Laser-irradiation method and laser-irradiation device | Dec 9, 2002 | Issued |