Eric Frank Winakur

Array ( [id] => 15772707 [patent_doc_number] => 20200117371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => DETERMINING A READ APPARENT VOLTAGE INFECTOR PAGE AND INFECTED PAGE [patent_app_type] => utility [patent_app_number] => 16/157597 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15120791 [patent_doc_number] => 20190347028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => METHOD FOR PERFORMING PAGE AVAILABILITY MANAGEMENT OF MEMORY DEVICE, ASSOCIATED MEMORY DEVICE AND ELECTRONIC DEVICE, AND PAGE AVAILABILITY MANAGEMENT SYSTEM [patent_app_type] => utility [patent_app_number] => 16/141983 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16141983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15609949 [patent_doc_number] => 10586039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Information processing apparatus [patent_app_type] => utility [patent_app_number] => 16/111694 [patent_app_country] => US [patent_app_date] => 2018-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 12856 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16111694 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14506179 [patent_doc_number] => 20190196744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => NONVOLATILE MEMORY DEVICE, METHOD OF OPERATING NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/111813 [patent_app_country] => US [patent_app_date] => 2018-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12504 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16111813 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16263293 [patent_doc_number] => 10754726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Tracking error-correction parity calculations [patent_app_type] => utility [patent_app_number] => 16/107187 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16416611 [patent_doc_number] => 10824505 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-03 [patent_title] => ECC proxy extension and byte organization for multi-master systems [patent_app_type] => utility [patent_app_number] => 16/106691 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4848 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16106691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14286767 [patent_doc_number] => 20190140668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME FOR ADAPTIVE ERROR CHECK AND CORRECTION [patent_app_type] => utility [patent_app_number] => 16/104497 [patent_app_country] => US [patent_app_date] => 2018-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16104497 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16371148 [patent_doc_number] => 10802909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Enhanced bit flipping scheme [patent_app_type] => utility [patent_app_number] => 16/104470 [patent_app_country] => US [patent_app_date] => 2018-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 17377 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16104470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17374585 [patent_doc_number] => 20220029637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => METHOD FOR ENCODING AND DECODING LDPC CODE AND COMMUNICATION APPARATUS THEREFOR [patent_app_type] => utility [patent_app_number] => 17/261423 [patent_app_country] => US [patent_app_date] => 2018-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17261423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13539531 [patent_doc_number] => 20180321312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => TEST DEVICE [patent_app_type] => utility [patent_app_number] => 16/039880 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16039880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13544519 [patent_doc_number] => 20180323806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => SLIDING WINDOW LIST DECODER FOR ERROR CORRECTING CODES [patent_app_type] => utility [patent_app_number] => 16/036206 [patent_app_country] => US [patent_app_date] => 2018-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16036206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13787257 [patent_doc_number] => 20190007167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => METHODS FOR REDUCING DATA ERRORS IN TRANSCEIVING OF A FLASH STORAGE INTERFACE AND APPARATUSES USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/013091 [patent_app_country] => US [patent_app_date] => 2018-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16013091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15886973 [patent_doc_number] => 10649831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Processor and memory access method [patent_app_type] => utility [patent_app_number] => 16/011685 [patent_app_country] => US [patent_app_date] => 2018-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 15132 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16011685 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16147755 [patent_doc_number] => 10706952 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-07 [patent_title] => Testing for memories during mission mode self-test [patent_app_type] => utility [patent_app_number] => 16/012455 [patent_app_country] => US [patent_app_date] => 2018-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16012455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16667214 [patent_doc_number] => 10936460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Method and apparatus for identifying and reporting faults at an information handling system [patent_app_type] => utility [patent_app_number] => 16/012324 [patent_app_country] => US [patent_app_date] => 2018-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16012324 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16387370 [patent_doc_number] => 10812223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Method for efficient packet framing in a communication network [patent_app_type] => utility [patent_app_number] => 16/004477 [patent_app_country] => US [patent_app_date] => 2018-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7297 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16004477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15809081 [patent_doc_number] => 20200127683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => SIMPLIFIED, PRESORTED, SYNDROME-BASED, EXTENDED MIN-SUM (EMS) DECODING OF NON-BINARY LDPC CODES [patent_app_type] => utility [patent_app_number] => 16/622410 [patent_app_country] => US [patent_app_date] => 2018-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16622410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13416065 [patent_doc_number] => 20180259575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => TEST MODE CONTROL CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/976607 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7707 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17700858 [patent_doc_number] => 11374594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Apparatus and method including neural network learning to detect and correct quantum errors [patent_app_type] => utility [patent_app_number] => 15/972114 [patent_app_country] => US [patent_app_date] => 2018-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 8369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15972114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13406625 [patent_doc_number] => 20180254855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => APPARATUS AND METHOD FOR SENDING AND RECEIVING BROADCAST SIGNALS [patent_app_type] => utility [patent_app_number] => 15/971238 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15971238 [rel_patent_id] =>[rel_patent_doc_number] =>)