Search

Eric Frank Winakur

Examiner (ID: 185, Phone: (571)272-4736 , Office: P/3777 )

Most Active Art Unit
3736
Art Unit(s)
3791, 3735, 3768, 3777, 2899, 3311, 3736
Total Applications
2497
Issued Applications
1849
Pending Applications
331
Abandoned Applications
337

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19633490 [patent_doc_number] => 20240411939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => RECOVERING DATA FROM DE-SEQUENCED ENCODED DATA SLICES [patent_app_type] => utility [patent_app_number] => 18/808433 [patent_app_country] => US [patent_app_date] => 2024-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18808433 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/808433
RECOVERING DATA FROM DE-SEQUENCED ENCODED DATA SLICES Aug 18, 2024 Issued
Array ( [id] => 19756388 [patent_doc_number] => 20250044953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => ERROR DETECTION FOR PROGRAMMING SINGLE LEVEL CELLS [patent_app_type] => utility [patent_app_number] => 18/797445 [patent_app_country] => US [patent_app_date] => 2024-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18797445 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/797445
ERROR DETECTION FOR PROGRAMMING SINGLE LEVEL CELLS Aug 6, 2024 Pending
Array ( [id] => 19756592 [patent_doc_number] => 20250045157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => REAL TIME SYNDROME CHECK [patent_app_type] => utility [patent_app_number] => 18/795992 [patent_app_country] => US [patent_app_date] => 2024-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18795992 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/795992
REAL TIME SYNDROME CHECK Aug 5, 2024 Pending
Array ( [id] => 20461966 [patent_doc_number] => 20260011395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-08 [patent_title] => TESTING METHOD AND TESTING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/791443 [patent_app_country] => US [patent_app_date] => 2024-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18791443 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/791443
Testing method and testing system Jul 31, 2024 Issued
Array ( [id] => 19590754 [patent_doc_number] => 20240388311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => TWO-LEVEL ERROR CORRECTING CODE WITH SHARING OF CHECK-BITS [patent_app_type] => utility [patent_app_number] => 18/789063 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789063 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/789063
TWO-LEVEL ERROR CORRECTING CODE WITH SHARING OF CHECK-BITS Jul 29, 2024 Pending
Array ( [id] => 20502371 [patent_doc_number] => 20260031834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => ERROR DECODING WITH ITERATIVE PARAMETER UPDATING [patent_app_type] => utility [patent_app_number] => 18/783001 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783001 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/783001
ERROR DECODING WITH ITERATIVE PARAMETER UPDATING Jul 23, 2024 Pending
Array ( [id] => 20124289 [patent_doc_number] => 20250239320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => ERROR CORRECTION DISABLEMENT BY A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/776867 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776867 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/776867
ERROR CORRECTION DISABLEMENT BY A MEMORY SYSTEM Jul 17, 2024 Pending
Array ( [id] => 20487448 [patent_doc_number] => 20260023647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => READ THRESHOLD MANAGEMENT USING PAGE TYPE [patent_app_type] => utility [patent_app_number] => 18/775848 [patent_app_country] => US [patent_app_date] => 2024-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6533 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18775848 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/775848
READ THRESHOLD MANAGEMENT USING PAGE TYPE Jul 16, 2024 Issued
Array ( [id] => 19747138 [patent_doc_number] => 20250035703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => SCAN-SHIFT BUFFER ISOLATOR FOR DYNAMIC POWER REDUCTION [patent_app_type] => utility [patent_app_number] => 18/770967 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770967 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770967
SCAN-SHIFT BUFFER ISOLATOR FOR DYNAMIC POWER REDUCTION Jul 11, 2024 Pending
Array ( [id] => 19697422 [patent_doc_number] => 20250015967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => CONFIGURATION SCHEME FOR LINK ESTABLISHMENT [patent_app_type] => utility [patent_app_number] => 18/768851 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768851 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768851
CONFIGURATION SCHEME FOR LINK ESTABLISHMENT Jul 9, 2024 Pending
Array ( [id] => 20063107 [patent_doc_number] => 20250201329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => DETECTING ERRORS WITHIN DATA PATH CIRCUITRY OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/766219 [patent_app_country] => US [patent_app_date] => 2024-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766219 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/766219
Detecting errors within data path circuitry of a memory device Jul 7, 2024 Issued
Array ( [id] => 20455787 [patent_doc_number] => 12518847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Centralized error correction circuit [patent_app_type] => utility [patent_app_number] => 18/647867 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14576 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647867 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647867
Centralized error correction circuit Jun 6, 2024 Issued
Array ( [id] => 19696119 [patent_doc_number] => 20250014664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => STORAGE DEVICE DETERMINING DETERIORATION WORDLINE, AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/677544 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677544 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677544
STORAGE DEVICE DETERMINING DETERIORATION WORDLINE, AND METHOD OF OPERATING THE SAME May 28, 2024 Pending
Array ( [id] => 20550408 [patent_doc_number] => 12561201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Error protection for managed memory devices [patent_app_type] => utility [patent_app_number] => 18/672533 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 13669 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672533 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672533
Error protection for managed memory devices May 22, 2024 Issued
Array ( [id] => 20360647 [patent_doc_number] => 12476655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Low-density parity check decoder [patent_app_type] => utility [patent_app_number] => 18/664711 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 3780 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664711 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664711
Low-density parity check decoder May 14, 2024 Issued
Array ( [id] => 20565257 [patent_doc_number] => 12567872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => LDPC decoder and minimum value searching method [patent_app_type] => utility [patent_app_number] => 18/664686 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2558 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664686 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664686
LDPC decoder and minimum value searching method May 14, 2024 Issued
Array ( [id] => 20368138 [patent_doc_number] => 20250357950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => DECODING A SIGNAL BASED ON SOFT SYNDROME DECODING TECHNIQUES [patent_app_type] => utility [patent_app_number] => 18/663882 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663882 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663882
DECODING A SIGNAL BASED ON SOFT SYNDROME DECODING TECHNIQUES May 13, 2024 Pending
Array ( [id] => 20551951 [patent_doc_number] => 12562754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Single-index parity check for polar encoding [patent_app_type] => utility [patent_app_number] => 18/653759 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14978 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653759 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653759
Single-index parity check for polar encoding May 1, 2024 Issued
Array ( [id] => 20010883 [patent_doc_number] => 20250149105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => MEMORY DEVICE FOR SUPPORTING TRIPLE ADJACENT ERROR DETECTION, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/648882 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648882 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648882
MEMORY DEVICE FOR SUPPORTING TRIPLE ADJACENT ERROR DETECTION, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF Apr 28, 2024 Pending
Array ( [id] => 20674535 [patent_doc_number] => 12615062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-28 [patent_title] => Systems and methods for block-kronecker based low density parity check (LDPC) code with 3/4 code rate [patent_app_type] => utility [patent_app_number] => 18/647792 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15958 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647792 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647792
Systems and methods for block-kronecker based low density parity check (LDPC) code with 3/4 code rate Apr 25, 2024 Issued
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