Search

Eric Frank Winakur

Examiner (ID: 185, Phone: (571)272-4736 , Office: P/3777 )

Most Active Art Unit
3736
Art Unit(s)
3791, 3735, 3768, 3777, 2899, 3311, 3736
Total Applications
2497
Issued Applications
1849
Pending Applications
331
Abandoned Applications
337

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9645131 [patent_doc_number] => 20140223244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'FLASH STORAGE DEVICE WITH READ DISTURB MITIGATION' [patent_app_type] => utility [patent_app_number] => 14/257978 [patent_app_country] => US [patent_app_date] => 2014-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14257978 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/257978
Flash storage device with read disturb mitigation Apr 20, 2014 Issued
Array ( [id] => 9658790 [patent_doc_number] => 20140229795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'CONFIGURABLE CODING SYSTEM AND METHOD OF MULTIPLE ECCS' [patent_app_type] => utility [patent_app_number] => 14/254530 [patent_app_country] => US [patent_app_date] => 2014-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3110 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14254530 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/254530
CONFIGURABLE CODING SYSTEM AND METHOD OF MULTIPLE ECCS Apr 15, 2014 Abandoned
Array ( [id] => 11917315 [patent_doc_number] => 09785501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Error detection and handling for a data storage device' [patent_app_type] => utility [patent_app_number] => 14/182567 [patent_app_country] => US [patent_app_date] => 2014-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12699 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14182567 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/182567
Error detection and handling for a data storage device Feb 17, 2014 Issued
Array ( [id] => 10351719 [patent_doc_number] => 20150236724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'Dynamically Controlling Erasure Code Distribution In An Object Store' [patent_app_type] => utility [patent_app_number] => 14/183310 [patent_app_country] => US [patent_app_date] => 2014-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7964 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14183310 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/183310
Dynamically controlling erasure code distribution in an object store Feb 17, 2014 Issued
Array ( [id] => 10047193 [patent_doc_number] => 09087591 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-21 [patent_title] => 'Method and apparatus for detecting valid data using selective modification of cyclic redundancy codes' [patent_app_type] => utility [patent_app_number] => 14/177063 [patent_app_country] => US [patent_app_date] => 2014-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 12440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14177063 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/177063
Method and apparatus for detecting valid data using selective modification of cyclic redundancy codes Feb 9, 2014 Issued
Array ( [id] => 9866746 [patent_doc_number] => 20150046766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 14/386868 [patent_app_country] => US [patent_app_date] => 2014-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 124 [patent_figures_cnt] => 124 [patent_no_of_words] => 53745 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14386868 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/386868
DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD Jan 26, 2014 Abandoned
Array ( [id] => 10928080 [patent_doc_number] => 20140331101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-06 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHOD OF WRITING DATA IN THE SAME' [patent_app_type] => utility [patent_app_number] => 14/160614 [patent_app_country] => US [patent_app_date] => 2014-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12560 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14160614 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/160614
Semiconductor memory devices, memory systems including the same and method of writing data in the same Jan 21, 2014 Issued
Array ( [id] => 10320661 [patent_doc_number] => 20150205665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'ECC METHOD FOR FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 14/158613 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14158613 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/158613
ECC method for flash memory Jan 16, 2014 Issued
Array ( [id] => 10309200 [patent_doc_number] => 20150194201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'REAL TIME CORRECTION OF BIT FAILURE IN RESISTIVE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/150559 [patent_app_country] => US [patent_app_date] => 2014-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7320 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14150559 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/150559
Real time correction of bit failure in resistive memory Jan 7, 2014 Issued
Array ( [id] => 10300285 [patent_doc_number] => 20150185285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'SYSTEM AND METHOD FOR REDUCED PIN LOGIC SCANNING' [patent_app_type] => utility [patent_app_number] => 14/143821 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8692 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143821 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/143821
SYSTEM AND METHOD FOR REDUCED PIN LOGIC SCANNING Dec 29, 2013 Abandoned
Array ( [id] => 11686511 [patent_doc_number] => 09684558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-20 [patent_title] => 'Accessing data stored in a dispersed storage memory' [patent_app_type] => utility [patent_app_number] => 14/107157 [patent_app_country] => US [patent_app_date] => 2013-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 14489 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14107157 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/107157
Accessing data stored in a dispersed storage memory Dec 15, 2013 Issued
Array ( [id] => 9800847 [patent_doc_number] => 20150012791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'PARALLEL TEST DEVICE AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/074820 [patent_app_country] => US [patent_app_date] => 2013-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6509 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074820 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/074820
Parallel test device and method Nov 7, 2013 Issued
Array ( [id] => 10228354 [patent_doc_number] => 20150113348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'IMPLEMENTING MISR COMPRESSION METHODS FOR TEST TIME REDUCTION' [patent_app_type] => utility [patent_app_number] => 14/060744 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14060744 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/060744
Implementing MISR compression methods for test time reduction Oct 22, 2013 Issued
Array ( [id] => 9800848 [patent_doc_number] => 20150012792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'METHOD AND APPARATUS FOR PROVIDING A TRANSMISSION CONTROL PROTOCOL MINIMUM RETRANSMISSION TIMER' [patent_app_type] => utility [patent_app_number] => 14/061259 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3029 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061259 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/061259
METHOD AND APPARATUS FOR PROVIDING A TRANSMISSION CONTROL PROTOCOL MINIMUM RETRANSMISSION TIMER Oct 22, 2013 Abandoned
Array ( [id] => 9604923 [patent_doc_number] => 20140201605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'SIGNAL RECEPTION APPARATUS, BLOCK DECODING UNIT AND METHOD THEREOF IN RADIO COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/061142 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5540 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061142 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/061142
SIGNAL RECEPTION APPARATUS, BLOCK DECODING UNIT AND METHOD THEREOF IN RADIO COMMUNICATION SYSTEM Oct 22, 2013 Abandoned
Array ( [id] => 11412404 [patent_doc_number] => 09559725 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-31 [patent_title] => 'Multi-strength reed-solomon outer code protection' [patent_app_type] => utility [patent_app_number] => 14/061344 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4285 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061344 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/061344
Multi-strength reed-solomon outer code protection Oct 22, 2013 Issued
Array ( [id] => 9814594 [patent_doc_number] => 20150026540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'FLASH DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/059615 [patent_app_country] => US [patent_app_date] => 2013-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3109 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14059615 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/059615
Flash device and operating method thereof Oct 21, 2013 Issued
Array ( [id] => 9451780 [patent_doc_number] => 20140122950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 14/059796 [patent_app_country] => US [patent_app_date] => 2013-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8085 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14059796 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/059796
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Oct 21, 2013 Abandoned
Array ( [id] => 11286281 [patent_doc_number] => 09502139 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-22 [patent_title] => 'Fine grained online remapping to handle memory errors' [patent_app_type] => utility [patent_app_number] => 14/058919 [patent_app_country] => US [patent_app_date] => 2013-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14058919 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/058919
Fine grained online remapping to handle memory errors Oct 20, 2013 Issued
Array ( [id] => 10046060 [patent_doc_number] => 09086454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Timing-aware test generation and fault simulation' [patent_app_type] => utility [patent_app_number] => 14/053322 [patent_app_country] => US [patent_app_date] => 2013-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 16486 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14053322 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/053322
Timing-aware test generation and fault simulation Oct 13, 2013 Issued
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