Search

Eric Frank Winakur

Examiner (ID: 185, Phone: (571)272-4736 , Office: P/3777 )

Most Active Art Unit
3736
Art Unit(s)
3791, 3735, 3768, 3777, 2899, 3311, 3736
Total Applications
2497
Issued Applications
1849
Pending Applications
331
Abandoned Applications
337

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8280181 [patent_doc_number] => 20120174049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'TIMING-AWARE TEST GENERATION AND FAULT SIMULATION' [patent_app_type] => utility [patent_app_number] => 13/285899 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 16445 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13285899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/285899
Timing-aware test generation and fault simulation Oct 30, 2011 Issued
Array ( [id] => 7759947 [patent_doc_number] => 20120030527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/251802 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5571 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20120030527.pdf [firstpage_image] =>[orig_patent_app_number] => 13251802 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251802
SEMICONDUCTOR MEMORY DEVICE Oct 2, 2011 Abandoned
Array ( [id] => 8965578 [patent_doc_number] => 20130205180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'FAULT DETECTION SYSTEM, ACQUISITION APPARATUS, FAULT DETECTION METHOD, PROGRAM, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 13/877601 [patent_app_country] => US [patent_app_date] => 2011-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12294 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13877601 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/877601
Fault detection system, acquisition apparatus, fault detection method, program, and non-transitory computer-readable medium Sep 27, 2011 Issued
Array ( [id] => 7563012 [patent_doc_number] => 20110276846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'UNINITIALIZED MEMORY DETECTION USING ERROR CORRECTION CODES AND BUILT-IN SELF TEST' [patent_app_type] => utility [patent_app_number] => 13/187657 [patent_app_country] => US [patent_app_date] => 2011-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6174 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20110276846.pdf [firstpage_image] =>[orig_patent_app_number] => 13187657 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/187657
Uninitialized memory detection using error correction codes and built-in self test Jul 20, 2011 Issued
Array ( [id] => 7575502 [patent_doc_number] => 20110271158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'METHOD AND APPARATUS FOR TESTING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 13/180301 [patent_app_country] => US [patent_app_date] => 2011-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3627 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20110271158.pdf [firstpage_image] =>[orig_patent_app_number] => 13180301 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/180301
Method and apparatus for testing high capacity/high bandwidth memory devices Jul 10, 2011 Issued
Array ( [id] => 8242565 [patent_doc_number] => 20120151301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/176030 [patent_app_country] => US [patent_app_date] => 2011-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8296 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13176030 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/176030
SEMICONDUCTOR MEMORY DEVICE Jul 4, 2011 Abandoned
Array ( [id] => 8588723 [patent_doc_number] => 20130007544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'MAPPING OF RANDOM DEFECTS IN A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/175801 [patent_app_country] => US [patent_app_date] => 2011-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6502 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13175801 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/175801
Mapping of random defects in a memory device Jun 30, 2011 Issued
Array ( [id] => 7665086 [patent_doc_number] => 20110314355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-22 [patent_title] => 'ACCESSING DATA STORED IN A DISPERSED STORAGE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/154167 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14388 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13154167 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/154167
Accessing data stored in a dispersed storage memory Jun 5, 2011 Issued
Array ( [id] => 9029729 [patent_doc_number] => 08539327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Semiconductor integrated circuit for testing logic circuit' [patent_app_type] => utility [patent_app_number] => 13/153681 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2482 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13153681 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/153681
Semiconductor integrated circuit for testing logic circuit Jun 5, 2011 Issued
Array ( [id] => 7665087 [patent_doc_number] => 20110314356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-22 [patent_title] => 'VERIFYING INTEGRITY OF DATA STORED IN A DISPERSED STORAGE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/154181 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14388 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13154181 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/154181
Verifying integrity of data stored in a dispersed storage memory Jun 5, 2011 Issued
Array ( [id] => 8574841 [patent_doc_number] => 08341503 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-25 [patent_title] => 'Methods and systems for storing data in memory using zoning' [patent_app_type] => utility [patent_app_number] => 13/151000 [patent_app_country] => US [patent_app_date] => 2011-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2635 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13151000 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/151000
Methods and systems for storing data in memory using zoning May 31, 2011 Issued
Array ( [id] => 8479271 [patent_doc_number] => 20120278679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'Iterating Inner and Outer Codes for Data Recovery' [patent_app_type] => utility [patent_app_number] => 13/094048 [patent_app_country] => US [patent_app_date] => 2011-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13094048 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/094048
Iterating inner and outer codes for data recovery Apr 25, 2011 Issued
Array ( [id] => 8479264 [patent_doc_number] => 20120278671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES' [patent_app_type] => utility [patent_app_number] => 13/093942 [patent_app_country] => US [patent_app_date] => 2011-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6686 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13093942 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/093942
Circuit and method for diagnosing scan chain failures Apr 25, 2011 Issued
Array ( [id] => 7714291 [patent_doc_number] => 20120005545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'Computer product, verification support apparatus, and verification support method' [patent_app_type] => utility [patent_app_number] => 13/064902 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 13140 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20120005545.pdf [firstpage_image] =>[orig_patent_app_number] => 13064902 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/064902
Verification support of circuit blocks having independent clock domains Apr 24, 2011 Issued
Array ( [id] => 8952809 [patent_doc_number] => 20130198590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'METHOD OF REDUCING PEAK-TO-AVERAGE POWER RATIO, CUBIC METRIC AND BLOCK ERROR RATE IN OFDM SYSTEMS USING NETWORK CODING' [patent_app_type] => utility [patent_app_number] => 13/642423 [patent_app_country] => US [patent_app_date] => 2011-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7497 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13642423 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/642423
Method of reducing peak-to-average power ratio, cubic metric and block error rate in OFDM systems using network coding Apr 20, 2011 Issued
Array ( [id] => 6210860 [patent_doc_number] => 20110134707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'BLOCK ISOLATION CONTROL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/024169 [patent_app_country] => US [patent_app_date] => 2011-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5312 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20110134707.pdf [firstpage_image] =>[orig_patent_app_number] => 13024169 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/024169
BLOCK ISOLATION CONTROL CIRCUIT Feb 8, 2011 Abandoned
Array ( [id] => 6006213 [patent_doc_number] => 20110119542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'SEMICONDUCTOR DEVICE TEST SYSTEM WITH TEST INTERFACE MEANS' [patent_app_type] => utility [patent_app_number] => 13/008517 [patent_app_country] => US [patent_app_date] => 2011-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7482 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20110119542.pdf [firstpage_image] =>[orig_patent_app_number] => 13008517 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/008517
Semiconductor device test system with test interface means Jan 17, 2011 Issued
Array ( [id] => 8280049 [patent_doc_number] => 20120173921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'REDUNDANCY MEMORY STORAGE SYSTEM AND A METHOD FOR CONTROLLING A REDUNDANCY MEMORY STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/985139 [patent_app_country] => US [patent_app_date] => 2011-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12985139 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/985139
REDUNDANCY MEMORY STORAGE SYSTEM AND A METHOD FOR CONTROLLING A REDUNDANCY MEMORY STORAGE SYSTEM Jan 4, 2011 Abandoned
Array ( [id] => 9102774 [patent_doc_number] => 08566668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-22 [patent_title] => 'Edge memory architecture for LDPC decoder' [patent_app_type] => utility [patent_app_number] => 12/984013 [patent_app_country] => US [patent_app_date] => 2011-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8670 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12984013 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/984013
Edge memory architecture for LDPC decoder Jan 3, 2011 Issued
Array ( [id] => 6153941 [patent_doc_number] => 20110022914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'Replacement messages for identifying and preventing errors during the transmission of realtime-critical data' [patent_app_type] => utility [patent_app_number] => 12/898770 [patent_app_country] => US [patent_app_date] => 2010-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2475 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20110022914.pdf [firstpage_image] =>[orig_patent_app_number] => 12898770 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/898770
Replacement messages for identifying and preventing errors during the transmission of realtime-critical data Oct 5, 2010 Issued
Menu