Search

Eric Frank Winakur

Examiner (ID: 185, Phone: (571)272-4736 , Office: P/3777 )

Most Active Art Unit
3736
Art Unit(s)
3791, 3735, 3768, 3777, 2899, 3311, 3736
Total Applications
2497
Issued Applications
1849
Pending Applications
331
Abandoned Applications
337

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9680580 [patent_doc_number] => 08819507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Field programmable gate arrays with built-in self test mechanisms' [patent_app_type] => utility [patent_app_number] => 12/777228 [patent_app_country] => US [patent_app_date] => 2010-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6934 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12777228 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/777228
Field programmable gate arrays with built-in self test mechanisms May 9, 2010 Issued
Array ( [id] => 8645692 [patent_doc_number] => 08370690 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-05 [patent_title] => 'Custom defined call quality versus battery life' [patent_app_type] => utility [patent_app_number] => 12/768865 [patent_app_country] => US [patent_app_date] => 2010-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5536 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12768865 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/768865
Custom defined call quality versus battery life Apr 27, 2010 Issued
Array ( [id] => 6463407 [patent_doc_number] => 20100281316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT, INFORMATION PROCESSING APPARATUS, OUTPUT DATA DIFFUSION METHOD, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/765476 [patent_app_country] => US [patent_app_date] => 2010-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10825 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281316.pdf [firstpage_image] =>[orig_patent_app_number] => 12765476 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/765476
SEMICONDUCTOR INTEGRATED CIRCUIT, INFORMATION PROCESSING APPARATUS, OUTPUT DATA DIFFUSION METHOD, AND PROGRAM Apr 21, 2010 Abandoned
Array ( [id] => 6241173 [patent_doc_number] => 20100269000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'METHODS AND APPARATUSES FOR MANAGING BAD MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 12/763626 [patent_app_country] => US [patent_app_date] => 2010-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5085 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20100269000.pdf [firstpage_image] =>[orig_patent_app_number] => 12763626 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/763626
METHODS AND APPARATUSES FOR MANAGING BAD MEMORY CELL Apr 19, 2010 Abandoned
Array ( [id] => 6100501 [patent_doc_number] => 20110004784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'DATA ACCESSING METHOD AND DATA ACCESSING SYSTEM UTILIZING THE METHOD' [patent_app_type] => utility [patent_app_number] => 12/754606 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20110004784.pdf [firstpage_image] =>[orig_patent_app_number] => 12754606 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754606
DATA ACCESSING METHOD AND DATA ACCESSING SYSTEM UTILIZING THE METHOD Apr 4, 2010 Abandoned
Array ( [id] => 6586101 [patent_doc_number] => 20100235695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'MEMORY APPARATUS AND TESTING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/722538 [patent_app_country] => US [patent_app_date] => 2010-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3510 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20100235695.pdf [firstpage_image] =>[orig_patent_app_number] => 12722538 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/722538
Memory apparatus and testing method thereof Mar 11, 2010 Issued
Array ( [id] => 6094111 [patent_doc_number] => 20110219266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'System and Method of Testing an Error Correction Module' [patent_app_type] => utility [patent_app_number] => 12/717165 [patent_app_country] => US [patent_app_date] => 2010-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4568 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20110219266.pdf [firstpage_image] =>[orig_patent_app_number] => 12717165 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/717165
System and Method of Testing an Error Correction Module Mar 3, 2010 Abandoned
Array ( [id] => 9555744 [patent_doc_number] => 08762818 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-24 [patent_title] => 'System and methods for performing decoding error detection in a storage device' [patent_app_type] => utility [patent_app_number] => 12/713520 [patent_app_country] => US [patent_app_date] => 2010-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12713520 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/713520
System and methods for performing decoding error detection in a storage device Feb 25, 2010 Issued
Array ( [id] => 5940201 [patent_doc_number] => 20110214040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'Method and System For Cyclic Redundancy Check' [patent_app_type] => utility [patent_app_number] => 12/713600 [patent_app_country] => US [patent_app_date] => 2010-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8571 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20110214040.pdf [firstpage_image] =>[orig_patent_app_number] => 12713600 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/713600
Method and system for cyclic redundancy check Feb 25, 2010 Issued
Array ( [id] => 6031843 [patent_doc_number] => 20110055662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'NESTED DISTRIBUTED STORAGE UNIT AND APPLICATIONS THEREOF' [patent_app_type] => utility [patent_app_number] => 12/712842 [patent_app_country] => US [patent_app_date] => 2010-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12609 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055662.pdf [firstpage_image] =>[orig_patent_app_number] => 12712842 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/712842
Nested distributed storage unit and applications thereof Feb 24, 2010 Issued
Array ( [id] => 6565111 [patent_doc_number] => 20100223514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/712529 [patent_app_country] => US [patent_app_date] => 2010-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5141 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20100223514.pdf [firstpage_image] =>[orig_patent_app_number] => 12712529 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/712529
SEMICONDUCTOR MEMORY DEVICE Feb 24, 2010 Abandoned
Array ( [id] => 6031841 [patent_doc_number] => 20110055661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'METHOD AND APPARATUS FOR NESTED DISBURSED STORAGE' [patent_app_type] => utility [patent_app_number] => 12/712773 [patent_app_country] => US [patent_app_date] => 2010-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12611 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055661.pdf [firstpage_image] =>[orig_patent_app_number] => 12712773 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/712773
Method and apparatus for nested dispersed storage Feb 24, 2010 Issued
Array ( [id] => 8849338 [patent_doc_number] => 08458538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Latency detection in a memory built-in self-test by using a ping signal' [patent_app_type] => utility [patent_app_number] => 12/709605 [patent_app_country] => US [patent_app_date] => 2010-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8587 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12709605 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/709605
Latency detection in a memory built-in self-test by using a ping signal Feb 21, 2010 Issued
Array ( [id] => 6524294 [patent_doc_number] => 20100211820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'Method of managing non-volatile memory device and memory system including the same' [patent_app_type] => utility [patent_app_number] => 12/656718 [patent_app_country] => US [patent_app_date] => 2010-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7923 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20100211820.pdf [firstpage_image] =>[orig_patent_app_number] => 12656718 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/656718
Method of managing non-volatile memory device and memory system including the same Feb 15, 2010 Abandoned
Array ( [id] => 8087631 [patent_doc_number] => 08151150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-03 [patent_title] => 'Data storage device and method for writing test data to a memory' [patent_app_type] => utility [patent_app_number] => 12/705644 [patent_app_country] => US [patent_app_date] => 2010-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4054 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/151/08151150.pdf [firstpage_image] =>[orig_patent_app_number] => 12705644 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/705644
Data storage device and method for writing test data to a memory Feb 14, 2010 Issued
Array ( [id] => 6414281 [patent_doc_number] => 20100306579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/700507 [patent_app_country] => US [patent_app_date] => 2010-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3863 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0306/20100306579.pdf [firstpage_image] =>[orig_patent_app_number] => 12700507 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/700507
NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME Feb 3, 2010 Abandoned
Array ( [id] => 6337172 [patent_doc_number] => 20100199018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'DATA TRANSFER SYSTEM, DATA TRANSMITTING APPARATUS, DATA RECEIVING APPARATUS, AND DATA TRANSFER METHOD' [patent_app_type] => utility [patent_app_number] => 12/698867 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11624 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20100199018.pdf [firstpage_image] =>[orig_patent_app_number] => 12698867 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698867
DATA TRANSFER SYSTEM, DATA TRANSMITTING APPARATUS, DATA RECEIVING APPARATUS, AND DATA TRANSFER METHOD Feb 1, 2010 Abandoned
Array ( [id] => 6586070 [patent_doc_number] => 20100235692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'MEMORY TEST CIRCUIT AND PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/695358 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15068 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20100235692.pdf [firstpage_image] =>[orig_patent_app_number] => 12695358 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/695358
MEMORY TEST CIRCUIT AND PROCESSOR Jan 27, 2010 Abandoned
Array ( [id] => 6153919 [patent_doc_number] => 20110022907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'FPGA Test Configuration Minimization' [patent_app_type] => utility [patent_app_number] => 12/689791 [patent_app_country] => US [patent_app_date] => 2010-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2946 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20110022907.pdf [firstpage_image] =>[orig_patent_app_number] => 12689791 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/689791
FPGA Test Configuration Minimization Jan 18, 2010 Abandoned
Array ( [id] => 6182181 [patent_doc_number] => 20110179325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'SYSTEM FOR BOUNDARY SCAN REGISTER CHAIN COMPRESSION' [patent_app_type] => utility [patent_app_number] => 12/687893 [patent_app_country] => US [patent_app_date] => 2010-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3223 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20110179325.pdf [firstpage_image] =>[orig_patent_app_number] => 12687893 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/687893
SYSTEM FOR BOUNDARY SCAN REGISTER CHAIN COMPRESSION Jan 14, 2010 Abandoned
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