Search

Eric Frank Winakur

Examiner (ID: 185, Phone: (571)272-4736 , Office: P/3777 )

Most Active Art Unit
3736
Art Unit(s)
3791, 3735, 3768, 3777, 2899, 3311, 3736
Total Applications
2497
Issued Applications
1849
Pending Applications
331
Abandoned Applications
337

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6409799 [patent_doc_number] => 20100180167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'ELECTRONIC CONTROL APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/652220 [patent_app_country] => US [patent_app_date] => 2010-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5647 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20100180167.pdf [firstpage_image] =>[orig_patent_app_number] => 12652220 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/652220
Electronic control apparatus Jan 4, 2010 Issued
Array ( [id] => 6234393 [patent_doc_number] => 20100185909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'Asynchronous Scan Chain Circuit' [patent_app_type] => utility [patent_app_number] => 12/651919 [patent_app_country] => US [patent_app_date] => 2010-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4543 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20100185909.pdf [firstpage_image] =>[orig_patent_app_number] => 12651919 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/651919
Asynchronous Scan Chain Circuit Jan 3, 2010 Abandoned
Array ( [id] => 6166731 [patent_doc_number] => 20110161752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'ROBUST MEMORY LINK TESTING USING MEMORY CONTROLLER' [patent_app_type] => utility [patent_app_number] => 12/651252 [patent_app_country] => US [patent_app_date] => 2009-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3884 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20110161752.pdf [firstpage_image] =>[orig_patent_app_number] => 12651252 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/651252
Robust memory link testing using memory controller Dec 30, 2009 Issued
Array ( [id] => 6647187 [patent_doc_number] => 20100174954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'NON-POLYNOMIAL PROCESSING UNIT FOR SOFT-DECISION ERROR CORRECTION CODING' [patent_app_type] => utility [patent_app_number] => 12/651386 [patent_app_country] => US [patent_app_date] => 2009-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7126 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20100174954.pdf [firstpage_image] =>[orig_patent_app_number] => 12651386 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/651386
Non-polynomial processing unit for soft-decision error correction coding Dec 30, 2009 Issued
Array ( [id] => 6330701 [patent_doc_number] => 20100327877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'RADIO FREQUENCY IDENTIFICATION (RFID) DEVICE AND METHOD FOR TESTING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/650524 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 70 [patent_no_of_words] => 33106 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20100327877.pdf [firstpage_image] =>[orig_patent_app_number] => 12650524 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650524
RADIO FREQUENCY IDENTIFICATION (RFID) DEVICE AND METHOD FOR TESTING THE SAME Dec 29, 2009 Abandoned
Array ( [id] => 8087625 [patent_doc_number] => 08151149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-03 [patent_title] => 'Semiconductor memory apparatus and method of testing the same' [patent_app_type] => utility [patent_app_number] => 12/649743 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4827 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/151/08151149.pdf [firstpage_image] =>[orig_patent_app_number] => 12649743 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/649743
Semiconductor memory apparatus and method of testing the same Dec 29, 2009 Issued
Array ( [id] => 7768321 [patent_doc_number] => 08117508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Non-volatile memory device and programming method thereof' [patent_app_type] => utility [patent_app_number] => 12/650006 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 7682 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/117/08117508.pdf [firstpage_image] =>[orig_patent_app_number] => 12650006 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650006
Non-volatile memory device and programming method thereof Dec 29, 2009 Issued
Array ( [id] => 8594964 [patent_doc_number] => 08352847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Matrix vector multiplication for error-correction encoding and the like' [patent_app_type] => utility [patent_app_number] => 12/644161 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10475 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12644161 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/644161
Matrix vector multiplication for error-correction encoding and the like Dec 21, 2009 Issued
Array ( [id] => 6449920 [patent_doc_number] => 20100153800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'LOGIC TESTER AND METHOD FOR SIMULTANEOUSLY MEASURING DELAY PERIODS OF MULTIPLE TESTED DEVICES' [patent_app_type] => utility [patent_app_number] => 12/638368 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2582 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20100153800.pdf [firstpage_image] =>[orig_patent_app_number] => 12638368 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/638368
Logic tester and method for simultaneously measuring delay periods of multiple tested devices Dec 14, 2009 Issued
Array ( [id] => 9251901 [patent_doc_number] => 08615692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-24 [patent_title] => 'Method and system for analyzing test vectors to determine toggle counts' [patent_app_type] => utility [patent_app_number] => 12/637935 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7654 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12637935 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/637935
Method and system for analyzing test vectors to determine toggle counts Dec 14, 2009 Issued
Array ( [id] => 6449887 [patent_doc_number] => 20100153797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'Apparatus and method of authenticating Joint Test Action Group (JTAG)' [patent_app_type] => utility [patent_app_number] => 12/653082 [patent_app_country] => US [patent_app_date] => 2009-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3552 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20100153797.pdf [firstpage_image] =>[orig_patent_app_number] => 12653082 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/653082
Apparatus and method of authenticating joint test action group (JTAG) Dec 7, 2009 Issued
Array ( [id] => 7547977 [patent_doc_number] => 08055958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Replacement data storage circuit storing address of defective memory cell' [patent_app_type] => utility [patent_app_number] => 12/630094 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7061 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/055/08055958.pdf [firstpage_image] =>[orig_patent_app_number] => 12630094 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630094
Replacement data storage circuit storing address of defective memory cell Dec 2, 2009 Issued
Array ( [id] => 6388702 [patent_doc_number] => 20100083074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'Block Code Decoding Method And Device Thereof' [patent_app_type] => utility [patent_app_number] => 12/567558 [patent_app_country] => US [patent_app_date] => 2009-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5270 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20100083074.pdf [firstpage_image] =>[orig_patent_app_number] => 12567558 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/567558
Block code decoding method and device thereof Sep 24, 2009 Issued
Array ( [id] => 5981917 [patent_doc_number] => 20110072333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'CONTROL METHOD FOR FLASH MEMORY BASED ON VARIABLE LENGTH ECC' [patent_app_type] => utility [patent_app_number] => 12/566627 [patent_app_country] => US [patent_app_date] => 2009-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1720 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20110072333.pdf [firstpage_image] =>[orig_patent_app_number] => 12566627 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/566627
CONTROL METHOD FOR FLASH MEMORY BASED ON VARIABLE LENGTH ECC Sep 23, 2009 Abandoned
Array ( [id] => 6204124 [patent_doc_number] => 20110066910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'STEALTH MESSAGE TRANSMISSION IN A NETWORK' [patent_app_type] => utility [patent_app_number] => 12/560665 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20110066910.pdf [firstpage_image] =>[orig_patent_app_number] => 12560665 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/560665
Stealth message transmission in a network Sep 15, 2009 Issued
Array ( [id] => 6302403 [patent_doc_number] => 20100162055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'MEMORY SYSTEM, TRANSFER CONTROLLER, AND MEMORY CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 12/558718 [patent_app_country] => US [patent_app_date] => 2009-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7410 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20100162055.pdf [firstpage_image] =>[orig_patent_app_number] => 12558718 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558718
MEMORY SYSTEM, TRANSFER CONTROLLER, AND MEMORY CONTROL METHOD Sep 13, 2009 Abandoned
Array ( [id] => 6204120 [patent_doc_number] => 20110066906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'Pulse Triggered Latches with Scan Functionality' [patent_app_type] => utility [patent_app_number] => 12/558754 [patent_app_country] => US [patent_app_date] => 2009-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5023 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20110066906.pdf [firstpage_image] =>[orig_patent_app_number] => 12558754 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558754
Pulse Triggered Latches with Scan Functionality Sep 13, 2009 Abandoned
Array ( [id] => 6312812 [patent_doc_number] => 20100070827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'ERROR CORRECTION CIRCUIT, FLASH MEMORY SYSTEM INCLUDING THE ERROR CORRECTION CIRCUIT, AND OPERATING METHOD OF THE ERROR CORRECTION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/556822 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5382 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20100070827.pdf [firstpage_image] =>[orig_patent_app_number] => 12556822 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556822
Error correction circuit, flash memory system including the error correction circuit, and operating method of the error correction circuit Sep 9, 2009 Issued
Array ( [id] => 8716202 [patent_doc_number] => 08402353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Cyclic code processing circuit, network interface card, and cyclic code processing method' [patent_app_type] => utility [patent_app_number] => 12/557269 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 20779 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12557269 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/557269
Cyclic code processing circuit, network interface card, and cyclic code processing method Sep 9, 2009 Issued
Array ( [id] => 8593412 [patent_doc_number] => 08351290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-08 [patent_title] => 'Erased page detection' [patent_app_type] => utility [patent_app_number] => 12/557311 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 12447 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12557311 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/557311
Erased page detection Sep 9, 2009 Issued
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