Eric Frank Winakur

Array ( [id] => 5448128 [patent_doc_number] => 20090049354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'Single-pass, concurrent-validation methods for generating test patterns for sequential circuits' [patent_app_type] => utility [patent_app_number] => 11/893683 [patent_app_country] => US [patent_app_date] => 2007-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20090049354.pdf [firstpage_image] =>[orig_patent_app_number] => 11893683 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5362989 [patent_doc_number] => 20090037783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'PROTECTING DATA STORAGE STRUCTURES FROM INTERMITTENT ERRORS' [patent_app_type] => utility [patent_app_number] => 11/833765 [patent_app_country] => US [patent_app_date] => 2007-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3232 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037783.pdf [firstpage_image] =>[orig_patent_app_number] => 11833765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4798988 [patent_doc_number] => 20080010574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'INTEGRATED CIRCUIT ARRANGEMENT AND METHOD FOR OPERATING AN INTEGRATED CIRCUIT ARRANGEMENT' [patent_app_type] => utility [patent_app_number] => 11/763140 [patent_app_country] => US [patent_app_date] => 2007-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2716 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20080010574.pdf [firstpage_image] =>[orig_patent_app_number] => 11763140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4934056 [patent_doc_number] => 20080004831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Circuitry and Method for an At-Speed Scan Test' [patent_app_type] => utility [patent_app_number] => 11/762353 [patent_app_country] => US [patent_app_date] => 2007-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20080004831.pdf [firstpage_image] =>[orig_patent_app_number] => 11762353 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7530042 [patent_doc_number] => 08046648 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-25 [patent_title] => 'Method and apparatus for controlling operating modes of an electronic device' [patent_app_type] => utility [patent_app_number] => 11/761815 [patent_app_country] => US [patent_app_date] => 2007-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11739 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/046/08046648.pdf [firstpage_image] =>[orig_patent_app_number] => 11761815 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5009536 [patent_doc_number] => 20070280014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/806122 [patent_app_country] => US [patent_app_date] => 2007-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1897 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20070280014.pdf [firstpage_image] =>[orig_patent_app_number] => 11806122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4923804 [patent_doc_number] => 20080072121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Method and Apparatus For Repairing Defective Cell for Each Cell Section Word Line' [patent_app_type] => utility [patent_app_number] => 11/750527 [patent_app_country] => US [patent_app_date] => 2007-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3712 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072121.pdf [firstpage_image] =>[orig_patent_app_number] => 11750527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5200789 [patent_doc_number] => 20070300107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Device test apparatus' [patent_app_type] => utility [patent_app_number] => 11/798635 [patent_app_country] => US [patent_app_date] => 2007-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3914 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20070300107.pdf [firstpage_image] =>[orig_patent_app_number] => 11798635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7510582 [patent_doc_number] => 08037371 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-11 [patent_title] => 'Apparatus and method for testing high-speed serial transmitters and other devices' [patent_app_type] => utility [patent_app_number] => 11/803231 [patent_app_country] => US [patent_app_date] => 2007-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/037/08037371.pdf [firstpage_image] =>[orig_patent_app_number] => 11803231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5167219 [patent_doc_number] => 20070288808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Method and system for detecting of errors within optical storage media' [patent_app_type] => utility [patent_app_number] => 11/798073 [patent_app_country] => US [patent_app_date] => 2007-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5327 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20070288808.pdf [firstpage_image] =>[orig_patent_app_number] => 11798073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5132579 [patent_doc_number] => 20070208976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'LOW OVERHEAD INPUT AND OUTPUT BOUNDARY SCAN CELLS' [patent_app_type] => utility [patent_app_number] => 11/745532 [patent_app_country] => US [patent_app_date] => 2007-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10270 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20070208976.pdf [firstpage_image] =>[orig_patent_app_number] => 11745532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 76652 [patent_doc_number] => 07757138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-13 [patent_title] => 'Semiconductor integrated circuit, test data generating device, LSI test device, and computer product' [patent_app_type] => utility [patent_app_number] => 11/797347 [patent_app_country] => US [patent_app_date] => 2007-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 8618 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/757/07757138.pdf [firstpage_image] =>[orig_patent_app_number] => 11797347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5167230 [patent_doc_number] => 20070288819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Semiconductor integrated circuit, test data generating device, lsi test device, and computer product' [patent_app_type] => utility [patent_app_number] => 11/797348 [patent_app_country] => US [patent_app_date] => 2007-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8213 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20070288819.pdf [firstpage_image] =>[orig_patent_app_number] => 11797348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4793977 [patent_doc_number] => 20080294951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'Methods and devices for testing computer memory' [patent_app_type] => utility [patent_app_number] => 11/797146 [patent_app_country] => US [patent_app_date] => 2007-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3545 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20080294951.pdf [firstpage_image] =>[orig_patent_app_number] => 11797146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8878807 [patent_doc_number] => 08473791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Redundant memory to mask DRAM failures' [patent_app_type] => utility [patent_app_number] => 11/742446 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2530 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11742446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4862366 [patent_doc_number] => 20080270828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Memory Redundancy Method and Apparatus' [patent_app_type] => utility [patent_app_number] => 11/741337 [patent_app_country] => US [patent_app_date] => 2007-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3135 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270828.pdf [firstpage_image] =>[orig_patent_app_number] => 11741337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7537709 [patent_doc_number] => 08051352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Timing-aware test generation and fault simulation' [patent_app_type] => utility [patent_app_number] => 11/796374 [patent_app_country] => US [patent_app_date] => 2007-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 16454 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/051/08051352.pdf [firstpage_image] =>[orig_patent_app_number] => 11796374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4862400 [patent_doc_number] => 20080270846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Methods and Apparatus for Compiling and Displaying Test Data Items' [patent_app_type] => utility [patent_app_number] => 11/740746 [patent_app_country] => US [patent_app_date] => 2007-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2865 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270846.pdf [firstpage_image] =>[orig_patent_app_number] => 11740746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4730710 [patent_doc_number] => 20080209294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'BUILT-IN SELF TESTING OF A FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 11/740314 [patent_app_country] => US [patent_app_date] => 2007-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4568 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209294.pdf [firstpage_image] =>[orig_patent_app_number] => 11740314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4862433 [patent_doc_number] => 20080270854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'SYSTEM AND METHOD FOR RUNNING TEST AND REDUNDANCY ANALYSIS IN PARALLEL' [patent_app_type] => utility [patent_app_number] => 11/739599 [patent_app_country] => US [patent_app_date] => 2007-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3630 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270854.pdf [firstpage_image] =>[orig_patent_app_number] => 11739599 [rel_patent_id] =>[rel_patent_doc_number] =>)