
Eric Frank Winakur
Examiner (ID: 185, Phone: (571)272-4736 , Office: P/3777 )
| Most Active Art Unit | 3736 |
| Art Unit(s) | 3791, 3735, 3768, 3777, 2899, 3311, 3736 |
| Total Applications | 2497 |
| Issued Applications | 1849 |
| Pending Applications | 331 |
| Abandoned Applications | 337 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5058717
[patent_doc_number] => 20070061639
[patent_country] => US
[patent_kind] => A1
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[patent_title] => 'Semiconductor device test system with test interface means'
[patent_app_type] => utility
[patent_app_number] => 11/513964
[patent_app_country] => US
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[pdf_file] => publications/A1/0061/20070061639.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/513964 | Semiconductor device test system with test interface means | Aug 30, 2006 | Issued |
Array
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[patent_issue_date] => 2008-03-20
[patent_title] => 'Yield-Enhancing Device Failure Analysis'
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Array
(
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[patent_title] => 'Allowable bit errors per sector in memory devices'
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Array
(
[id] => 321470
[patent_doc_number] => 07523373
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[patent_kind] => B2
[patent_issue_date] => 2009-04-21
[patent_title] => 'Minimum memory operating voltage technique'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/468458 | Minimum memory operating voltage technique | Aug 29, 2006 | Issued |
Array
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Array
(
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[patent_title] => 'Sub-instruction repeats for algorithmic pattern generators'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/513087 | Sub-instruction repeats for algorithmic pattern generators | Aug 29, 2006 | Issued |
Array
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[patent_title] => 'APPARATUS AND METHOD FOR TESTING MEMORY DEVICES AND CIRCUITS IN INTEGRATED CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 11/465864
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Array
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[patent_issue_date] => 2007-03-15
[patent_title] => 'SEMICONDUCTOR DEVICE WITH TEST INTERFACE'
[patent_app_type] => utility
[patent_app_number] => 11/465540
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/465540 | Semiconductor device with test interface | Aug 17, 2006 | Issued |
Array
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[id] => 4984454
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[patent_title] => 'SYSTEM AND METHOD FOR TESTING PORTS OF A COMPUTER'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/309339 | SYSTEM AND METHOD FOR TESTING PORTS OF A COMPUTER | Jul 27, 2006 | Abandoned |
Array
(
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[patent_title] => 'Memory module and method thereof'
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[patent_app_number] => 11/489446
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/489446 | Memory module and method thereof | Jul 19, 2006 | Abandoned |
Array
(
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[patent_title] => 'Cell supporting scan-based tests and with reduced time delay in functional mode'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/309191 | Cell supporting scan-based tests and with reduced time delay in functional mode | Jul 11, 2006 | Issued |
Array
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Array
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Array
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Array
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Array
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Array
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