Search

Eric Frank Winakur

Examiner (ID: 185, Phone: (571)272-4736 , Office: P/3777 )

Most Active Art Unit
3736
Art Unit(s)
3791, 3735, 3768, 3777, 2899, 3311, 3736
Total Applications
2497
Issued Applications
1849
Pending Applications
331
Abandoned Applications
337

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5058717 [patent_doc_number] => 20070061639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Semiconductor device test system with test interface means' [patent_app_type] => utility [patent_app_number] => 11/513964 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20070061639.pdf [firstpage_image] =>[orig_patent_app_number] => 11513964 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/513964
Semiconductor device test system with test interface means Aug 30, 2006 Issued
Array ( [id] => 4923801 [patent_doc_number] => 20080072118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Yield-Enhancing Device Failure Analysis' [patent_app_type] => utility [patent_app_number] => 11/468838 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5338 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072118.pdf [firstpage_image] =>[orig_patent_app_number] => 11468838 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/468838
Yield-enhancing device failure analysis Aug 30, 2006 Issued
Array ( [id] => 4923802 [patent_doc_number] => 20080072119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Allowable bit errors per sector in memory devices' [patent_app_type] => utility [patent_app_number] => 11/515048 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2432 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072119.pdf [firstpage_image] =>[orig_patent_app_number] => 11515048 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/515048
Allowable bit errors per sector in memory devices Aug 30, 2006 Abandoned
Array ( [id] => 321470 [patent_doc_number] => 07523373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-21 [patent_title] => 'Minimum memory operating voltage technique' [patent_app_type] => utility [patent_app_number] => 11/468458 [patent_app_country] => US [patent_app_date] => 2006-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7175 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/523/07523373.pdf [firstpage_image] =>[orig_patent_app_number] => 11468458 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/468458
Minimum memory operating voltage technique Aug 29, 2006 Issued
Array ( [id] => 5058699 [patent_doc_number] => 20070061621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Fault diagnosis apparatus and method for system-on-chip (SoC) and SoC in which fault is capable of being diagnosed' [patent_app_type] => utility [patent_app_number] => 11/512375 [patent_app_country] => US [patent_app_date] => 2006-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4239 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20070061621.pdf [firstpage_image] =>[orig_patent_app_number] => 11512375 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/512375
Fault diagnosis apparatus and method for system-on-chip (SoC) and SoC in which fault is capable of being diagnosed Aug 29, 2006 Abandoned
Array ( [id] => 4945559 [patent_doc_number] => 20080082886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Sub-instruction repeats for algorithmic pattern generators' [patent_app_type] => utility [patent_app_number] => 11/513087 [patent_app_country] => US [patent_app_date] => 2006-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6124 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20080082886.pdf [firstpage_image] =>[orig_patent_app_number] => 11513087 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/513087
Sub-instruction repeats for algorithmic pattern generators Aug 29, 2006 Issued
Array ( [id] => 4671728 [patent_doc_number] => 20080046789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'APPARATUS AND METHOD FOR TESTING MEMORY DEVICES AND CIRCUITS IN INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/465864 [patent_app_country] => US [patent_app_date] => 2006-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20080046789.pdf [firstpage_image] =>[orig_patent_app_number] => 11465864 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465864
APPARATUS AND METHOD FOR TESTING MEMORY DEVICES AND CIRCUITS IN INTEGRATED CIRCUITS Aug 20, 2006 Abandoned
Array ( [id] => 5058728 [patent_doc_number] => 20070061650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'SEMICONDUCTOR DEVICE WITH TEST INTERFACE' [patent_app_type] => utility [patent_app_number] => 11/465540 [patent_app_country] => US [patent_app_date] => 2006-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3108 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20070061650.pdf [firstpage_image] =>[orig_patent_app_number] => 11465540 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465540
Semiconductor device with test interface Aug 17, 2006 Issued
Array ( [id] => 4984454 [patent_doc_number] => 20070089013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'SYSTEM AND METHOD FOR TESTING PORTS OF A COMPUTER' [patent_app_type] => utility [patent_app_number] => 11/309339 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2256 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20070089013.pdf [firstpage_image] =>[orig_patent_app_number] => 11309339 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/309339
SYSTEM AND METHOD FOR TESTING PORTS OF A COMPUTER Jul 27, 2006 Abandoned
Array ( [id] => 5050270 [patent_doc_number] => 20070030814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Memory module and method thereof' [patent_app_type] => utility [patent_app_number] => 11/489446 [patent_app_country] => US [patent_app_date] => 2006-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6784 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20070030814.pdf [firstpage_image] =>[orig_patent_app_number] => 11489446 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/489446
Memory module and method thereof Jul 19, 2006 Abandoned
Array ( [id] => 37682 [patent_doc_number] => 07793178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Cell supporting scan-based tests and with reduced time delay in functional mode' [patent_app_type] => utility [patent_app_number] => 11/309191 [patent_app_country] => US [patent_app_date] => 2006-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 5024 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/793/07793178.pdf [firstpage_image] =>[orig_patent_app_number] => 11309191 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/309191
Cell supporting scan-based tests and with reduced time delay in functional mode Jul 11, 2006 Issued
Array ( [id] => 27454 [patent_doc_number] => 07802157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Test mode for multi-chip integrated circuit packages' [patent_app_type] => utility [patent_app_number] => 11/472618 [patent_app_country] => US [patent_app_date] => 2006-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4564 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/802/07802157.pdf [firstpage_image] =>[orig_patent_app_number] => 11472618 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/472618
Test mode for multi-chip integrated circuit packages Jun 21, 2006 Issued
Array ( [id] => 5200800 [patent_doc_number] => 20070300118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Method and system for controlling multiple physical pin electronics channels in a semiconductor test head' [patent_app_type] => utility [patent_app_number] => 11/448385 [patent_app_country] => US [patent_app_date] => 2006-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3464 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20070300118.pdf [firstpage_image] =>[orig_patent_app_number] => 11448385 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/448385
Method and system for controlling multiple physical pin electronics channels in a semiconductor test head Jun 5, 2006 Abandoned
Array ( [id] => 7530049 [patent_doc_number] => 08046655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Area efficient memory architecture with decoder self test and debug capability' [patent_app_type] => utility [patent_app_number] => 11/437420 [patent_app_country] => US [patent_app_date] => 2006-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4233 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/046/08046655.pdf [firstpage_image] =>[orig_patent_app_number] => 11437420 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/437420
Area efficient memory architecture with decoder self test and debug capability May 17, 2006 Issued
Array ( [id] => 5852991 [patent_doc_number] => 20060236182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Scan-based self-test structure and method using weighted scan-enable signals' [patent_app_type] => utility [patent_app_number] => 11/368015 [patent_app_country] => US [patent_app_date] => 2006-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6868 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20060236182.pdf [firstpage_image] =>[orig_patent_app_number] => 11368015 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/368015
Scan-based self-test structure and method using weighted scan-enable signals Mar 2, 2006 Issued
Array ( [id] => 5190505 [patent_doc_number] => 20070168814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Device and method for testing and for diagnosing digital circuits' [patent_app_type] => utility [patent_app_number] => 11/364369 [patent_app_country] => US [patent_app_date] => 2006-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11953 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20070168814.pdf [firstpage_image] =>[orig_patent_app_number] => 11364369 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/364369
Device and method for testing and for diagnosing digital circuits Feb 28, 2006 Issued
Array ( [id] => 5132571 [patent_doc_number] => 20070208968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'At-speed multi-port memory array test method and apparatus' [patent_app_type] => utility [patent_app_number] => 11/365648 [patent_app_country] => US [patent_app_date] => 2006-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3837 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20070208968.pdf [firstpage_image] =>[orig_patent_app_number] => 11365648 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/365648
At-speed multi-port memory array test method and apparatus Feb 28, 2006 Abandoned
Array ( [id] => 5674019 [patent_doc_number] => 20060179374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Wireless hardware debugging' [patent_app_type] => utility [patent_app_number] => 11/348745 [patent_app_country] => US [patent_app_date] => 2006-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3982 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20060179374.pdf [firstpage_image] =>[orig_patent_app_number] => 11348745 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/348745
Wireless hardware debugging Feb 6, 2006 Abandoned
Array ( [id] => 5102420 [patent_doc_number] => 20070185682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Time-aware trigger distribution' [patent_app_type] => utility [patent_app_number] => 11/348741 [patent_app_country] => US [patent_app_date] => 2006-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4455 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20070185682.pdf [firstpage_image] =>[orig_patent_app_number] => 11348741 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/348741
Time-aware trigger distribution Feb 5, 2006 Abandoned
Array ( [id] => 8878812 [patent_doc_number] => 08473796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Error detection in compressed data' [patent_app_type] => utility [patent_app_number] => 11/342177 [patent_app_country] => US [patent_app_date] => 2006-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4094 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11342177 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/342177
Error detection in compressed data Jan 26, 2006 Issued
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