Eric Frank Winakur

Array ( [id] => 4479530 [patent_doc_number] => 07945829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/795842 [patent_app_country] => US [patent_app_date] => 2006-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 21038 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/945/07945829.pdf [firstpage_image] =>[orig_patent_app_number] => 11795842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5215031 [patent_doc_number] => 20070104111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Internal analog loopback for a high-speed interface test' [patent_app_type] => utility [patent_app_number] => 11/267436 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3743 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20070104111.pdf [firstpage_image] =>[orig_patent_app_number] => 11267436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5746863 [patent_doc_number] => 20060109794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Communication system' [patent_app_type] => utility [patent_app_number] => 11/261622 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3669 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20060109794.pdf [firstpage_image] =>[orig_patent_app_number] => 11261622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5809461 [patent_doc_number] => 20060095817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Buffer for testing a memory module and method thereof' [patent_app_type] => utility [patent_app_number] => 11/260318 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6190 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095817.pdf [firstpage_image] =>[orig_patent_app_number] => 11260318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5036675 [patent_doc_number] => 20070101214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Self-testing apparatus with controllable environmental stress screening (ESS)' [patent_app_type] => utility [patent_app_number] => 11/261038 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7029 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20070101214.pdf [firstpage_image] =>[orig_patent_app_number] => 11261038 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 598951 [patent_doc_number] => 07447962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'JTAG interface using existing I/O bus' [patent_app_type] => utility [patent_app_number] => 11/255150 [patent_app_country] => US [patent_app_date] => 2005-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 14173 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/447/07447962.pdf [firstpage_image] =>[orig_patent_app_number] => 11255150 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5042272 [patent_doc_number] => 20070094554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Chip specific test mode execution on a memory module' [patent_app_type] => utility [patent_app_number] => 11/253716 [patent_app_country] => US [patent_app_date] => 2005-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20070094554.pdf [firstpage_image] =>[orig_patent_app_number] => 11253716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 66576 [patent_doc_number] => 07765450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'Methods for distribution of test generation programs' [patent_app_type] => utility [patent_app_number] => 11/256211 [patent_app_country] => US [patent_app_date] => 2005-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 13997 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/765/07765450.pdf [firstpage_image] =>[orig_patent_app_number] => 11256211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4984434 [patent_doc_number] => 20070088993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Memory tester having master/slave configuration' [patent_app_type] => utility [patent_app_number] => 11/252435 [patent_app_country] => US [patent_app_date] => 2005-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3302 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20070088993.pdf [firstpage_image] =>[orig_patent_app_number] => 11252435 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5195315 [patent_doc_number] => 20070083800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'System and method for varying test signal durations and assert times for testing memory devices' [patent_app_type] => utility [patent_app_number] => 11/248724 [patent_app_country] => US [patent_app_date] => 2005-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5525 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20070083800.pdf [firstpage_image] =>[orig_patent_app_number] => 11248724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5816624 [patent_doc_number] => 20060085715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Test board of semiconductor tester having modified input/output printed circuit pattern and testing method using the same' [patent_app_type] => utility [patent_app_number] => 11/243053 [patent_app_country] => US [patent_app_date] => 2005-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3624 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20060085715.pdf [firstpage_image] =>[orig_patent_app_number] => 11243053 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5190500 [patent_doc_number] => 20070168809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Systems and methods for LBIST testing using commonly controlled LBIST satellites' [patent_app_type] => utility [patent_app_number] => 11/199972 [patent_app_country] => US [patent_app_date] => 2005-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6445 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20070168809.pdf [firstpage_image] =>[orig_patent_app_number] => 11199972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5273662 [patent_doc_number] => 20090077438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'CIRCUIT INTERCONNECT TESTING ARRANGEMENT AND APPROACH THEREFOR' [patent_app_type] => utility [patent_app_number] => 11/572808 [patent_app_country] => US [patent_app_date] => 2005-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4966 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077438.pdf [firstpage_image] =>[orig_patent_app_number] => 11572808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5243842 [patent_doc_number] => 20070022337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Method and apparatus to verify non-deterministic results in an efficient random manner' [patent_app_type] => utility [patent_app_number] => 11/171783 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3084 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20070022337.pdf [firstpage_image] =>[orig_patent_app_number] => 11171783 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5243849 [patent_doc_number] => 20070022344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Digital storage element architecture comprising dual scan clocks and gated scan output' [patent_app_type] => utility [patent_app_number] => 11/171537 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11681 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20070022344.pdf [firstpage_image] =>[orig_patent_app_number] => 11171537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 605114 [patent_doc_number] => 07434152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Multiple-level data compression read mode for memory testing' [patent_app_type] => utility [patent_app_number] => 11/127810 [patent_app_country] => US [patent_app_date] => 2005-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8280 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/434/07434152.pdf [firstpage_image] =>[orig_patent_app_number] => 11127810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 305834 [patent_doc_number] => 07536617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Programmable in-situ delay fault test clock generator' [patent_app_type] => utility [patent_app_number] => 11/103877 [patent_app_country] => US [patent_app_date] => 2005-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4813 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/536/07536617.pdf [firstpage_image] =>[orig_patent_app_number] => 11103877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5696045 [patent_doc_number] => 20060156192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/102715 [patent_app_country] => US [patent_app_date] => 2005-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5524 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20060156192.pdf [firstpage_image] =>[orig_patent_app_number] => 11102715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5812211 [patent_doc_number] => 20060083084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Semiconductor test system' [patent_app_type] => utility [patent_app_number] => 11/081684 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7414 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20060083084.pdf [firstpage_image] =>[orig_patent_app_number] => 11081684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5684442 [patent_doc_number] => 20060200712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'System and method for testing memory' [patent_app_type] => utility [patent_app_number] => 11/070970 [patent_app_country] => US [patent_app_date] => 2005-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5685 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20060200712.pdf [firstpage_image] =>[orig_patent_app_number] => 11070970 [rel_patent_id] =>[rel_patent_doc_number] =>)