Search

Eric Frank Winakur

Examiner (ID: 185, Phone: (571)272-4736 , Office: P/3777 )

Most Active Art Unit
3736
Art Unit(s)
3791, 3735, 3768, 3777, 2899, 3311, 3736
Total Applications
2497
Issued Applications
1849
Pending Applications
331
Abandoned Applications
337

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18711728 [patent_doc_number] => 20230334357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => PREPARATION OF QUBITS [patent_app_type] => utility [patent_app_number] => 17/659277 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17659277 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/659277
Preparation of qubits Apr 13, 2022 Issued
Array ( [id] => 17964576 [patent_doc_number] => 20220345157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => MULTIBYTE ERROR DETECTION [patent_app_type] => utility [patent_app_number] => 17/719648 [patent_app_country] => US [patent_app_date] => 2022-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17719648 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/719648
MULTIBYTE ERROR DETECTION Apr 12, 2022 Abandoned
Array ( [id] => 18177267 [patent_doc_number] => 20230037996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/718422 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718422 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718422
Memory device and operating method thereof Apr 11, 2022 Issued
Array ( [id] => 20151612 [patent_doc_number] => 20250251450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => ADJUSTABLE TIMING EVENT MONITORING WINDOW [patent_app_type] => utility [patent_app_number] => 18/854443 [patent_app_country] => US [patent_app_date] => 2022-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18854443 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/854443
ADJUSTABLE TIMING EVENT MONITORING WINDOW Apr 4, 2022 Pending
Array ( [id] => 19567556 [patent_doc_number] => 12142333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Error correction in a memory device having an error correction code of a predetermined code rate [patent_app_type] => utility [patent_app_number] => 17/712550 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712550 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712550
Error correction in a memory device having an error correction code of a predetermined code rate Apr 3, 2022 Issued
Array ( [id] => 17753582 [patent_doc_number] => 20220231787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => PRIORITY BASED MAPPING OF ENCODED BITS TO SYMBOLS [patent_app_type] => utility [patent_app_number] => 17/657938 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17657938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/657938
Priority based mapping of encoded bits to symbols Apr 3, 2022 Issued
Array ( [id] => 18875375 [patent_doc_number] => 11863201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Correlation-based hardware sequence for layered decoding [patent_app_type] => utility [patent_app_number] => 17/711642 [patent_app_country] => US [patent_app_date] => 2022-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 20234 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17711642 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/711642
Correlation-based hardware sequence for layered decoding Mar 31, 2022 Issued
Array ( [id] => 18340120 [patent_doc_number] => 20230132069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => Serial Communications Module With CRC [patent_app_type] => utility [patent_app_number] => 17/710906 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7880 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710906 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/710906
Serial communications module with CRC Mar 30, 2022 Issued
Array ( [id] => 18316651 [patent_doc_number] => 11630732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Method of updating firmware of chip stably and effectively, firmware updating apparatus, and computer readable storage medium applying method [patent_app_type] => utility [patent_app_number] => 17/706808 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3913 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706808 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/706808
Method of updating firmware of chip stably and effectively, firmware updating apparatus, and computer readable storage medium applying method Mar 28, 2022 Issued
Array ( [id] => 17738895 [patent_doc_number] => 20220224357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => DATA PROCESSING METHOD AND DECODER [patent_app_type] => utility [patent_app_number] => 17/656945 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17656945 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/656945
DATA PROCESSING METHOD AND DECODER Mar 28, 2022 Abandoned
Array ( [id] => 18579578 [patent_doc_number] => 11736122 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-22 [patent_title] => Maximum-likelihood decoding of quantum codes [patent_app_type] => utility [patent_app_number] => 17/654545 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 12061 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654545 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654545
Maximum-likelihood decoding of quantum codes Mar 10, 2022 Issued
Array ( [id] => 17690224 [patent_doc_number] => 20220197517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => ASYNCHRONOUS POWER LOSS IMPACTED DATA STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/692683 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17692683 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/692683
Asynchronous power loss impacted data structure Mar 10, 2022 Issued
Array ( [id] => 18432184 [patent_doc_number] => 11677420 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-13 [patent_title] => Externalizing inter-symbol interference data in a data channel [patent_app_type] => utility [patent_app_number] => 17/683958 [patent_app_country] => US [patent_app_date] => 2022-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 12670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17683958 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/683958
Externalizing inter-symbol interference data in a data channel Feb 28, 2022 Issued
Array ( [id] => 18520640 [patent_doc_number] => 11710534 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-07-25 [patent_title] => Internal data availability for system debugging [patent_app_type] => utility [patent_app_number] => 17/682837 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 11593 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682837 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/682837
Internal data availability for system debugging Feb 27, 2022 Issued
Array ( [id] => 18371652 [patent_doc_number] => 11651833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Error detection in memory system [patent_app_type] => utility [patent_app_number] => 17/680128 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680128 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/680128
Error detection in memory system Feb 23, 2022 Issued
Array ( [id] => 17778677 [patent_doc_number] => 20220245027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => ENHANCED BIT FLIPPING SCHEME [patent_app_type] => utility [patent_app_number] => 17/674608 [patent_app_country] => US [patent_app_date] => 2022-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17674608 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/674608
Enhanced bit flipping scheme Feb 16, 2022 Issued
Array ( [id] => 18555968 [patent_doc_number] => 20230253985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => EFFICIENT DECODING SCHEMES FOR ERROR CORRECTING CODES FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/586290 [patent_app_country] => US [patent_app_date] => 2022-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17586290 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/586290
Efficient decoding schemes for error correcting codes for memory devices Jan 26, 2022 Issued
Array ( [id] => 17752493 [patent_doc_number] => 20220230698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => CENTRALIZED ERROR CORRECTION CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/647152 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19285 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647152 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/647152
Centralized error correction circuit Jan 4, 2022 Issued
Array ( [id] => 18521199 [patent_doc_number] => 11711098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Transmitter and parity permutation method thereof [patent_app_type] => utility [patent_app_number] => 17/563274 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 32517 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563274 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/563274
Transmitter and parity permutation method thereof Dec 27, 2021 Issued
Array ( [id] => 17691889 [patent_doc_number] => 20220199182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => INTEGRATED CIRCUIT WITH EMBEDDED MEMORY MODULES [patent_app_type] => utility [patent_app_number] => 17/644415 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2633 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17644415 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/644415
Integrated circuit with embedded memory modules Dec 14, 2021 Issued
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