Eric Nilsson

Array ( [id] => 7353599 [patent_doc_number] => 20040089889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Magnetic memory device having soft reference layer' [patent_app_type] => new [patent_app_number] => 10/697191 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4743 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20040089889.pdf [firstpage_image] =>[orig_patent_app_number] => 10697191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7353489 [patent_doc_number] => 20040089875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Heterojunction bipolar transistor' [patent_app_type] => new [patent_app_number] => 10/694889 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12948 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20040089875.pdf [firstpage_image] =>[orig_patent_app_number] => 10694889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7323369 [patent_doc_number] => 20040251481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Isolation region implant permitting improved photodiode structure' [patent_app_type] => new [patent_app_number] => 10/694990 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10183 [patent_no_of_claims] => 136 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20040251481.pdf [firstpage_image] =>[orig_patent_app_number] => 10694990 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 946835 [patent_doc_number] => 06965169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-15 [patent_title] => 'Hybrid integrated circuit package substrate' [patent_app_type] => utility [patent_app_number] => 10/692589 [patent_app_country] => US [patent_app_date] => 2003-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3177 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/965/06965169.pdf [firstpage_image] =>[orig_patent_app_number] => 10692589 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6990999 [patent_doc_number] => 20050090036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'ULTRA LOW DIELECTRIC CONSTANT THIN FILM' [patent_app_type] => utility [patent_app_number] => 10/691400 [patent_app_country] => US [patent_app_date] => 2003-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4646 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20050090036.pdf [firstpage_image] =>[orig_patent_app_number] => 10691400 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 767140 [patent_doc_number] => 07009236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Memory device with vertical transistors and deep trench capacitors and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/691173 [patent_app_country] => US [patent_app_date] => 2003-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2340 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/009/07009236.pdf [firstpage_image] =>[orig_patent_app_number] => 10691173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 954087 [patent_doc_number] => 06958502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-25 [patent_title] => 'Magnetic random access memory cell' [patent_app_type] => utility [patent_app_number] => 10/691300 [patent_app_country] => US [patent_app_date] => 2003-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4182 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958502.pdf [firstpage_image] =>[orig_patent_app_number] => 10691300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1140771 [patent_doc_number] => 06781164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'Semiconductor element' [patent_app_type] => B2 [patent_app_number] => 10/690290 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 5875 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/781/06781164.pdf [firstpage_image] =>[orig_patent_app_number] => 10690290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7393840 [patent_doc_number] => 20040173902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Ball grid array package stack' [patent_app_type] => new [patent_app_number] => 10/691240 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2557 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20040173902.pdf [firstpage_image] =>[orig_patent_app_number] => 10691240 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7154374 [patent_doc_number] => 20050082598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Storage device with charge trapping structure and methods' [patent_app_type] => utility [patent_app_number] => 10/689940 [patent_app_country] => US [patent_app_date] => 2003-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8040 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20050082598.pdf [firstpage_image] =>[orig_patent_app_number] => 10689940 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 756423 [patent_doc_number] => 07019402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Silicon chip carrier with through-vias using laser assisted chemical vapor deposition of conductor' [patent_app_type] => utility [patent_app_number] => 10/686640 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6635 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/019/07019402.pdf [firstpage_image] =>[orig_patent_app_number] => 10686640 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7189528 [patent_doc_number] => 20040084702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Magnetic memories with bit lines and digit lines that intersect at oblique angles and fabrication methods thereof' [patent_app_type] => new [patent_app_number] => 10/687134 [patent_app_country] => US [patent_app_date] => 2003-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7064 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20040084702.pdf [firstpage_image] =>[orig_patent_app_number] => 10687134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 783370 [patent_doc_number] => 06992330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Encapsulation of “top-emitting” OLED panels' [patent_app_type] => utility [patent_app_number] => 10/686890 [patent_app_country] => US [patent_app_date] => 2003-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4565 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/992/06992330.pdf [firstpage_image] =>[orig_patent_app_number] => 10686890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 975974 [patent_doc_number] => 06933591 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-23 [patent_title] => 'Electrically-programmable integrated circuit fuses and sensing circuits' [patent_app_type] => utility [patent_app_number] => 10/687199 [patent_app_country] => US [patent_app_date] => 2003-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 10060 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/933/06933591.pdf [firstpage_image] =>[orig_patent_app_number] => 10687199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 959011 [patent_doc_number] => 06953957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Charge transport material including a poly-3,3″-dialkyl-2,2′:5′2″-terthiophene' [patent_app_type] => utility [patent_app_number] => 10/684584 [patent_app_country] => US [patent_app_date] => 2003-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3153 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/953/06953957.pdf [firstpage_image] =>[orig_patent_app_number] => 10684584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 954128 [patent_doc_number] => 06958543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-25 [patent_title] => 'Semiconductor equipment with lateral and vertical MOS regions' [patent_app_type] => utility [patent_app_number] => 10/682890 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 6938 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958543.pdf [firstpage_image] =>[orig_patent_app_number] => 10682890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7612429 [patent_doc_number] => 06903407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-07 [patent_title] => 'Non volatile charge trapping dielectric memory cell structure with gate hole injection erase' [patent_app_type] => utility [patent_app_number] => 10/684890 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4986 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903407.pdf [firstpage_image] =>[orig_patent_app_number] => 10684890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1040912 [patent_doc_number] => 06870211 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-22 [patent_title] => 'Self-aligned array contact for memory cells' [patent_app_type] => utility [patent_app_number] => 10/605590 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4948 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/870/06870211.pdf [firstpage_image] =>[orig_patent_app_number] => 10605590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1085618 [patent_doc_number] => 06830963 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-14 [patent_title] => 'Fully depleted silicon-on-insulator CMOS logic' [patent_app_type] => B1 [patent_app_number] => 10/682590 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2995 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/830/06830963.pdf [firstpage_image] =>[orig_patent_app_number] => 10682590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 996835 [patent_doc_number] => 06914277 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-05 [patent_title] => 'Merged FinFET P-channel/N-channel pair' [patent_app_type] => utility [patent_app_number] => 10/674400 [patent_app_country] => US [patent_app_date] => 2003-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 3691 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914277.pdf [firstpage_image] =>[orig_patent_app_number] => 10674400 [rel_patent_id] =>[rel_patent_doc_number] =>)