Eric Raciti

Array ( [id] => 6692715 [patent_doc_number] => 20030040147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'LDMOS DEVICE WITH DOUBLE N-LAYERING AND PROCESS FOR ITS MANUFACTURE' [patent_app_type] => new [patent_app_number] => 10/266712 [patent_app_country] => US [patent_app_date] => 2002-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1488 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20030040147.pdf [firstpage_image] =>[orig_patent_app_number] => 10266712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1277574 [patent_doc_number] => 06645782 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Qualitative method for troubleshooting a dielectric tool' [patent_app_type] => B1 [patent_app_number] => 10/134084 [patent_app_country] => US [patent_app_date] => 2002-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2525 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/645/06645782.pdf [firstpage_image] =>[orig_patent_app_number] => 10134084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6696904 [patent_doc_number] => 20030109098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Method for making semiconductor device' [patent_app_type] => new [patent_app_number] => 10/114453 [patent_app_country] => US [patent_app_date] => 2002-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3982 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20030109098.pdf [firstpage_image] =>[orig_patent_app_number] => 10114453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6012397 [patent_doc_number] => 20020100980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/076344 [patent_app_country] => US [patent_app_date] => 2002-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 15415 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20020100980.pdf [firstpage_image] =>[orig_patent_app_number] => 10076344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1345897 [patent_doc_number] => 06582987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-24 [patent_title] => 'Method of fabricating microchannel array structure embedded in silicon substrate' [patent_app_type] => B2 [patent_app_number] => 10/022093 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3353 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/582/06582987.pdf [firstpage_image] =>[orig_patent_app_number] => 10022093 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6277202 [patent_doc_number] => 20020106888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Process for manufacturing an electronic semiconductor device with improved insulation by means of air gaps' [patent_app_type] => new [patent_app_number] => 10/006923 [patent_app_country] => US [patent_app_date] => 2001-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2136 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20020106888.pdf [firstpage_image] =>[orig_patent_app_number] => 10006923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1264307 [patent_doc_number] => 06660562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Method and apparatus for a lead-frame air-cavity package' [patent_app_type] => B2 [patent_app_number] => 09/998454 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3081 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660562.pdf [firstpage_image] =>[orig_patent_app_number] => 09998454 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6861252 [patent_doc_number] => 20030092260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'METHOD FOR FORMING A DUAL DAMASCENE APERTURE WHILE EMPLOYING A PERIPHERALLY LOCALIZED INTERMEDIATE ETCH STOP LAYER' [patent_app_type] => new [patent_app_number] => 09/990813 [patent_app_country] => US [patent_app_date] => 2001-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6101 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20030092260.pdf [firstpage_image] =>[orig_patent_app_number] => 09990813 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6692764 [patent_doc_number] => 20030040196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Method of forming insulation layer in semiconductor devices for controlling the composition and the doping concentration' [patent_app_type] => new [patent_app_number] => 09/984233 [patent_app_country] => US [patent_app_date] => 2001-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5869 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20030040196.pdf [firstpage_image] =>[orig_patent_app_number] => 09984233 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6618575 [patent_doc_number] => 20020064946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Field effect transistor with silicide gate' [patent_app_type] => new [patent_app_number] => 09/982653 [patent_app_country] => US [patent_app_date] => 2001-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1719 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20020064946.pdf [firstpage_image] =>[orig_patent_app_number] => 09982653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7645655 [patent_doc_number] => 06472314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Diamond barrier layer' [patent_app_type] => B1 [patent_app_number] => 09/968944 [patent_app_country] => US [patent_app_date] => 2001-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 2232 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472314.pdf [firstpage_image] =>[orig_patent_app_number] => 09968944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1418814 [patent_doc_number] => 06514883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-04 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/956554 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6951 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/514/06514883.pdf [firstpage_image] =>[orig_patent_app_number] => 09956554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6530700 [patent_doc_number] => 20020192934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => '2-input nor gate with NMOS transistors and PMOS transistors formed on different semiconductor layers' [patent_app_type] => new [patent_app_number] => 09/955303 [patent_app_country] => US [patent_app_date] => 2001-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4184 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20020192934.pdf [firstpage_image] =>[orig_patent_app_number] => 09955303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5813013 [patent_doc_number] => 20020038886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-04 [patent_title] => 'Method of forming trench transistor with self-aligned source' [patent_app_type] => new [patent_app_number] => 09/953054 [patent_app_country] => US [patent_app_date] => 2001-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4258 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20020038886.pdf [firstpage_image] =>[orig_patent_app_number] => 09953054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6476096 [patent_doc_number] => 20020024093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Semiconductor device with self-aligned contact structure employing dual spacers and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/933674 [patent_app_country] => US [patent_app_date] => 2001-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5700 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20020024093.pdf [firstpage_image] =>[orig_patent_app_number] => 09933674 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6716073 [patent_doc_number] => 20030027421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Method of locally forming metal silicide layers' [patent_app_type] => new [patent_app_number] => 09/917893 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1997 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20030027421.pdf [firstpage_image] =>[orig_patent_app_number] => 09917893 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6716072 [patent_doc_number] => 20030027420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Method for forming the partial salicide' [patent_app_type] => new [patent_app_number] => 09/917644 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3324 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20030027420.pdf [firstpage_image] =>[orig_patent_app_number] => 09917644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6716074 [patent_doc_number] => 20030027422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Method of locally forming metal silicide layers' [patent_app_type] => new [patent_app_number] => 09/917943 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1728 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20030027422.pdf [firstpage_image] =>[orig_patent_app_number] => 09917943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1500318 [patent_doc_number] => 06486034 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Method of forming LDMOS device with double N-layering' [patent_app_type] => B1 [patent_app_number] => 09/908824 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1458 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486034.pdf [firstpage_image] =>[orig_patent_app_number] => 09908824 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1332335 [patent_doc_number] => 06596599 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Gate stack for high performance sub-micron CMOS devices' [patent_app_type] => B1 [patent_app_number] => 09/905403 [patent_app_country] => US [patent_app_date] => 2001-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 7253 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/596/06596599.pdf [firstpage_image] =>[orig_patent_app_number] => 09905403 [rel_patent_id] =>[rel_patent_doc_number] =>)