Search

Eric T. Loonan

Examiner (ID: 2148, Phone: (571)272-6994 , Office: P/2131 )

Most Active Art Unit
2137
Art Unit(s)
2131, 2137, 2189, 2109
Total Applications
486
Issued Applications
285
Pending Applications
50
Abandoned Applications
160

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17128567 [patent_doc_number] => 20210303336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => Advanced Register Merging [patent_app_type] => utility [patent_app_number] => 17/217110 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12010 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17217110 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/217110
Advanced register merging Mar 29, 2021 Issued
Array ( [id] => 20482044 [patent_doc_number] => 12530519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Electrical circuit design inspection system and method [patent_app_type] => utility [patent_app_number] => 17/906832 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3204 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17906832 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/906832
Electrical circuit design inspection system and method Mar 24, 2021 Issued
Array ( [id] => 20703463 [patent_doc_number] => 12626176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Systems and methods for scalable quantum computing [patent_app_type] => utility [patent_app_number] => 17/913548 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2201 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17913548 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/913548
Systems and methods for scalable quantum computing Mar 24, 2021 Issued
Array ( [id] => 18031032 [patent_doc_number] => 11514222 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-29 [patent_title] => Cell-width aware buffer insertion technique for narrow channels [patent_app_type] => utility [patent_app_number] => 17/207266 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207266 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/207266
Cell-width aware buffer insertion technique for narrow channels Mar 18, 2021 Issued
Array ( [id] => 18047004 [patent_doc_number] => 11520960 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-06 [patent_title] => Register transfer level based side channel leakage assessment [patent_app_type] => utility [patent_app_number] => 17/201939 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6291 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17201939 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/201939
Register transfer level based side channel leakage assessment Mar 14, 2021 Issued
Array ( [id] => 16994324 [patent_doc_number] => 20210232744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS [patent_app_type] => utility [patent_app_number] => 17/187766 [patent_app_country] => US [patent_app_date] => 2021-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 191657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187766 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187766
Logic drive based on standard commodity FPGA IC chips Feb 26, 2021 Issued
Array ( [id] => 18072965 [patent_doc_number] => 11531799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Assessing performance of a hardware design using formal evaluation logic [patent_app_type] => utility [patent_app_number] => 17/184186 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13604 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184186
Assessing performance of a hardware design using formal evaluation logic Feb 23, 2021 Issued
Array ( [id] => 17977683 [patent_doc_number] => 11494545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Apparatus and method for advanced macro clock skewing [patent_app_type] => utility [patent_app_number] => 17/184184 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5296 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184184 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184184
Apparatus and method for advanced macro clock skewing Feb 23, 2021 Issued
Array ( [id] => 18415124 [patent_doc_number] => 11669667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Automatic test pattern generation (ATPG) for parametric faults [patent_app_type] => utility [patent_app_number] => 17/180013 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6273 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17180013 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/180013
Automatic test pattern generation (ATPG) for parametric faults Feb 18, 2021 Issued
Array ( [id] => 16887801 [patent_doc_number] => 20210173998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => Through-Silicon Vias in Integrated Circuit Packaging [patent_app_type] => utility [patent_app_number] => 17/179904 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179904 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/179904
Through-silicon vias in integrated circuit packaging Feb 18, 2021 Issued
Array ( [id] => 16887793 [patent_doc_number] => 20210173990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => OPTIMIZATION DEVICE AND METHOD OF CONTROLLING OPTIMIZATION DEVICE [patent_app_type] => utility [patent_app_number] => 17/178290 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178290 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/178290
Optimization device and method of controlling optimization device Feb 17, 2021 Issued
Array ( [id] => 17999942 [patent_doc_number] => 11501050 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-15 [patent_title] => Analog mixed-signal assertion-based checker system [patent_app_type] => utility [patent_app_number] => 17/176993 [patent_app_country] => US [patent_app_date] => 2021-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 10033 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17176993 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/176993
Analog mixed-signal assertion-based checker system Feb 15, 2021 Issued
Array ( [id] => 18235074 [patent_doc_number] => 11599633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-07 [patent_title] => Security information extraction and probe insertion for side-channel analysis [patent_app_type] => utility [patent_app_number] => 17/174436 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17174436 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/174436
Security information extraction and probe insertion for side-channel analysis Feb 11, 2021 Issued
Array ( [id] => 18302493 [patent_doc_number] => 11624387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Wall anchor for cart with recharging [patent_app_type] => utility [patent_app_number] => 17/172508 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 10689 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172508 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/172508
Wall anchor for cart with recharging Feb 9, 2021 Issued
Array ( [id] => 18760202 [patent_doc_number] => 11811246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Decentralized green-energy ecosystem [patent_app_type] => utility [patent_app_number] => 17/171482 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171482 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171482
Decentralized green-energy ecosystem Feb 8, 2021 Issued
Array ( [id] => 18015421 [patent_doc_number] => 11507719 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-22 [patent_title] => Accelerating formal property verification across design versions using sequential equivalence checking [patent_app_type] => utility [patent_app_number] => 17/170843 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 9507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17170843 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/170843
Accelerating formal property verification across design versions using sequential equivalence checking Feb 7, 2021 Issued
Array ( [id] => 17709577 [patent_doc_number] => 20220209585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => WIRELESS CHARGING CASE WITH A SHIELDED BATTERY [patent_app_type] => utility [patent_app_number] => 17/169820 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169820 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/169820
WIRELESS CHARGING CASE WITH A SHIELDED BATTERY Feb 7, 2021 Abandoned
Array ( [id] => 17940737 [patent_doc_number] => 11475193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Control path verification of hardware design for pipelined process [patent_app_type] => utility [patent_app_number] => 17/167698 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17167698 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/167698
Control path verification of hardware design for pipelined process Feb 3, 2021 Issued
Array ( [id] => 20305791 [patent_doc_number] => 12451795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Power converter, charging post and vehicle [patent_app_type] => utility [patent_app_number] => 17/794695 [patent_app_country] => US [patent_app_date] => 2021-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 0 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17794695 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/794695
Power converter, charging post and vehicle Jan 21, 2021 Issued
Array ( [id] => 18982625 [patent_doc_number] => 11907804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Federated quantum computing distributed architecture [patent_app_type] => utility [patent_app_number] => 17/140848 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 21208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140848 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/140848
Federated quantum computing distributed architecture Jan 3, 2021 Issued
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