Eric T. Loonan

Array ( [id] => 10015286 [patent_doc_number] => 09058300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Integrated circuits and methods to control access to multiple layers of memory' [patent_app_type] => utility [patent_app_number] => 12/069105 [patent_app_country] => US [patent_app_date] => 2008-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9153 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12069105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5437707 [patent_doc_number] => 20090172294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'Method and apparatus for supporting scalable coherence on many-core products through restricted exposure' [patent_app_type] => utility [patent_app_number] => 12/005785 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2908 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172294.pdf [firstpage_image] =>[orig_patent_app_number] => 12005785 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5437694 [patent_doc_number] => 20090172281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'Memory device and method for content virtualization' [patent_app_type] => utility [patent_app_number] => 12/005728 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2885 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172281.pdf [firstpage_image] =>[orig_patent_app_number] => 12005728 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9585748 [patent_doc_number] => 08775758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-08 [patent_title] => 'Memory device and method for performing a write-abort-safe firmware update' [patent_app_type] => utility [patent_app_number] => 12/005727 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3252 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12005727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5437743 [patent_doc_number] => 20090172330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'Protection of user-level applications based on page table information' [patent_app_type] => utility [patent_app_number] => 12/005681 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3000 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172330.pdf [firstpage_image] =>[orig_patent_app_number] => 12005681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4744559 [patent_doc_number] => 20080089161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'METHOD FOR TESTING FLASH MEMORY POWER LOSS RECOVERY' [patent_app_type] => utility [patent_app_number] => 11/953240 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5448 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20080089161.pdf [firstpage_image] =>[orig_patent_app_number] => 11953240 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11801476 [patent_doc_number] => 09542353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'System and method for reducing command scheduling constraints of memory circuits' [patent_app_type] => utility [patent_app_number] => 11/929225 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8503 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11929225 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4966782 [patent_doc_number] => 20080109602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'METHOD AND APPARATUS FOR WRITING DATA TO A DISK ARRAY' [patent_app_type] => utility [patent_app_number] => 11/928237 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5307 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109602.pdf [firstpage_image] =>[orig_patent_app_number] => 11928237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5332687 [patent_doc_number] => 20090113164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Method, System and Program Product for Address Translation Through an Intermediate Address Space' [patent_app_type] => utility [patent_app_number] => 11/928125 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3568 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20090113164.pdf [firstpage_image] =>[orig_patent_app_number] => 11928125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4868920 [patent_doc_number] => 20080147979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'CONFIGURABLE CACHE FOR A MICROPROCESSOR' [patent_app_type] => utility [patent_app_number] => 11/928242 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7796 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20080147979.pdf [firstpage_image] =>[orig_patent_app_number] => 11928242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4966775 [patent_doc_number] => 20080109595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/929261 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109595.pdf [firstpage_image] =>[orig_patent_app_number] => 11929261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4454902 [patent_doc_number] => 07966457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Configurable cache for a microprocessor' [patent_app_type] => utility [patent_app_number] => 11/928322 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7618 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966457.pdf [firstpage_image] =>[orig_patent_app_number] => 11928322 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4576323 [patent_doc_number] => 07822912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Flash storage chip and flash array storage system' [patent_app_type] => utility [patent_app_number] => 11/927708 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5822 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/822/07822912.pdf [firstpage_image] =>[orig_patent_app_number] => 11927708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5359583 [patent_doc_number] => 20090034377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'SYSTEM AND METHOD FOR EFFICIENT UPDATES OF SEQUENTIAL BLOCK STORAGE' [patent_app_type] => utility [patent_app_number] => 11/927952 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7159 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20090034377.pdf [firstpage_image] =>[orig_patent_app_number] => 11927952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4905542 [patent_doc_number] => 20080114956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'SYSTEM AND METHOD TO SECURE A COMPUTER SYSTEM BY SELECTIVE CONTROL OF WRITE ACCESS TO A DATA STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 11/858713 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5318 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20080114956.pdf [firstpage_image] =>[orig_patent_app_number] => 11858713 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4895240 [patent_doc_number] => 20080104340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Method of memory management' [patent_app_type] => utility [patent_app_number] => 11/902356 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3139 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20080104340.pdf [firstpage_image] =>[orig_patent_app_number] => 11902356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5510296 [patent_doc_number] => 20090083503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'SYSTEM OF CREATING LOGICAL VOLUME AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/858319 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3317 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20090083503.pdf [firstpage_image] =>[orig_patent_app_number] => 11858319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5029902 [patent_doc_number] => 20070271349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'SECURE STORAGE OF DATA IN A NETWORK' [patent_app_type] => utility [patent_app_number] => 11/834460 [patent_app_country] => US [patent_app_date] => 2007-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6756 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20070271349.pdf [firstpage_image] =>[orig_patent_app_number] => 11834460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4860961 [patent_doc_number] => 20080269811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'SCHEME FOR OVERWRITING STORED PHYSIOLOGICAL DATA IN AN IMPLANTABLE MEDICAL DEVICE' [patent_app_type] => utility [patent_app_number] => 11/740362 [patent_app_country] => US [patent_app_date] => 2007-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9545 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20080269811.pdf [firstpage_image] =>[orig_patent_app_number] => 11740362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5200696 [patent_doc_number] => 20070300014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Debug port for on-die DRAM' [patent_app_type] => utility [patent_app_number] => 11/785886 [patent_app_country] => US [patent_app_date] => 2007-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3162 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20070300014.pdf [firstpage_image] =>[orig_patent_app_number] => 11785886 [rel_patent_id] =>[rel_patent_doc_number] =>)