Search

Eric T. Loonan

Examiner (ID: 2148, Phone: (571)272-6994 , Office: P/2131 )

Most Active Art Unit
2137
Art Unit(s)
2131, 2137, 2189, 2109
Total Applications
486
Issued Applications
285
Pending Applications
50
Abandoned Applications
160

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12695146 [patent_doc_number] => 20180123548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => SIGNAL CHANNEL FOR REDUCING CROSSTALK NOISE, MODULE SUBSTRATE AND MEMORY MODULE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 15/720326 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9281 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720326 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/720326
Signal channel for reducing crosstalk noise, module substrate and memory module including the same Sep 28, 2017 Issued
Array ( [id] => 14734659 [patent_doc_number] => 10386726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Geometry vectorization for mask process correction [patent_app_type] => utility [patent_app_number] => 15/720182 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9639 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720182 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/720182
Geometry vectorization for mask process correction Sep 28, 2017 Issued
Array ( [id] => 14136231 [patent_doc_number] => 20190102505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => SEMICONDUCTOR PACKAGE FLOATING METAL CHECKS [patent_app_type] => utility [patent_app_number] => 15/719698 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719698 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/719698
Semiconductor package floating metal checks Sep 28, 2017 Issued
Array ( [id] => 14136233 [patent_doc_number] => 20190102506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => SEMICONDUCTOR PACKAGE METAL SHADOWING CHECKS [patent_app_type] => utility [patent_app_number] => 15/719743 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719743 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/719743
Semiconductor package metal shadowing checks Sep 28, 2017 Issued
Array ( [id] => 16444731 [patent_doc_number] => 10836642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Graphene semiconductor design method [patent_app_type] => utility [patent_app_number] => 16/476963 [patent_app_country] => US [patent_app_date] => 2017-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1894 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16476963 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/476963
Graphene semiconductor design method Sep 17, 2017 Issued
Array ( [id] => 13992985 [patent_doc_number] => 20190065650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => INTEGRATED CIRCUIT DESIGN AND/OR FABRICATION [patent_app_type] => utility [patent_app_number] => 15/690603 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690603 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690603
Integrated circuit design and/or fabrication Aug 29, 2017 Issued
Array ( [id] => 12629412 [patent_doc_number] => 20180101634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => DESIGN ASSISTANCE PROGRAMS, DESIGN ASSISTANCE METHODS, AND INFORMATION PROCESSING APPARATUSES [patent_app_type] => utility [patent_app_number] => 15/690491 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690491 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690491
Assistance programs, design assistance methods, and information processing apparatuses Aug 29, 2017 Issued
Array ( [id] => 13993251 [patent_doc_number] => 20190065783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => COMPUTATIONALLY IMPLEMENTED METHOD WITH ENABLED LOCKDOWN CODE AND CAPABILITY [patent_app_type] => utility [patent_app_number] => 15/690285 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690285 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690285
COMPUTATIONALLY IMPLEMENTED METHOD WITH ENABLED LOCKDOWN CODE AND CAPABILITY Aug 29, 2017 Abandoned
Array ( [id] => 14427775 [patent_doc_number] => 10318693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-11 [patent_title] => Balanced scaled-load clustering [patent_app_type] => utility [patent_app_number] => 15/690043 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690043 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690043
Balanced scaled-load clustering Aug 28, 2017 Issued
Array ( [id] => 14857291 [patent_doc_number] => 10417375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Time-driven placement and/or cloning of components for an integrated circuit [patent_app_type] => utility [patent_app_number] => 15/689791 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12559 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15689791 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/689791
Time-driven placement and/or cloning of components for an integrated circuit Aug 28, 2017 Issued
Array ( [id] => 16306920 [patent_doc_number] => 10775705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Patterning stack optimization [patent_app_type] => utility [patent_app_number] => 16/325228 [patent_app_country] => US [patent_app_date] => 2017-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 24046 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16325228 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/325228
Patterning stack optimization Aug 1, 2017 Issued
Array ( [id] => 14523953 [patent_doc_number] => 10339239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Reciprocal Quantum Logic (RQL) circuit simulation system [patent_app_type] => utility [patent_app_number] => 15/663778 [patent_app_country] => US [patent_app_date] => 2017-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6540 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15663778 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/663778
Reciprocal Quantum Logic (RQL) circuit simulation system Jul 29, 2017 Issued
Array ( [id] => 15982915 [patent_doc_number] => 10671789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Integrated circuit and layout method [patent_app_type] => utility [patent_app_number] => 15/655763 [patent_app_country] => US [patent_app_date] => 2017-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15655763 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/655763
Integrated circuit and layout method Jul 19, 2017 Issued
Array ( [id] => 16745455 [patent_doc_number] => 10970445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Methods and apparatus for performing timing driven hardware emulation [patent_app_type] => utility [patent_app_number] => 15/635951 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5402 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15635951 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/635951
Methods and apparatus for performing timing driven hardware emulation Jun 27, 2017 Issued
Array ( [id] => 15116081 [patent_doc_number] => 20190344673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => Secondary Unit, a System for Inductive Power Transfer and a Method for Operating a Secondary Unit and a System for Inductive Power Transfer [patent_app_type] => utility [patent_app_number] => 16/307246 [patent_app_country] => US [patent_app_date] => 2017-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16307246 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/307246
Secondary Unit, a System for Inductive Power Transfer and a Method for Operating a Secondary Unit and a System for Inductive Power Transfer Jun 13, 2017 Abandoned
Array ( [id] => 16802384 [patent_doc_number] => 10997331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Integrated circuit including parametric analog elements [patent_app_type] => utility [patent_app_number] => 15/609252 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 9297 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609252 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/609252
Integrated circuit including parametric analog elements May 30, 2017 Issued
Array ( [id] => 12263658 [patent_doc_number] => 20180082854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'METAL FILL OPTIMIZATION FOR SELF-ALIGNED DOUBLE PATTERNING' [patent_app_type] => utility [patent_app_number] => 15/604090 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15604090 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/604090
Metal fill optimization for self-aligned double patterning May 23, 2017 Issued
Array ( [id] => 18155343 [patent_doc_number] => 11568325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Learning apparatus, estimation apparatus, learning method, and program [patent_app_type] => utility [patent_app_number] => 16/606409 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6906 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16606409 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/606409
Learning apparatus, estimation apparatus, learning method, and program May 15, 2017 Issued
Array ( [id] => 14268823 [patent_doc_number] => 10283986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Methods and devices for presenting auxiliary energy delivery indicia on a display [patent_app_type] => utility [patent_app_number] => 15/592908 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 11398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592908 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/592908
Methods and devices for presenting auxiliary energy delivery indicia on a display May 10, 2017 Issued
Array ( [id] => 14126393 [patent_doc_number] => 10250066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Wireless charging autoclavable batteries inside a sterilizable tray [patent_app_type] => utility [patent_app_number] => 15/592678 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 45 [patent_no_of_words] => 14455 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592678 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/592678
Wireless charging autoclavable batteries inside a sterilizable tray May 10, 2017 Issued
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