Search

Eric T. Loonan

Examiner (ID: 2148, Phone: (571)272-6994 , Office: P/2131 )

Most Active Art Unit
2137
Art Unit(s)
2131, 2137, 2189, 2109
Total Applications
486
Issued Applications
285
Pending Applications
50
Abandoned Applications
160

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19284224 [patent_doc_number] => 20240220700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => PROCESS MODEL GENERATING METHOD, PROCESS PROXIMITY CORRECTION METHOD, AND COMPUTING DEVICE THEREFOR [patent_app_type] => utility [patent_app_number] => 18/210836 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18210836 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/210836
PROCESS MODEL GENERATING METHOD, PROCESS PROXIMITY CORRECTION METHOD, AND COMPUTING DEVICE THEREFOR Jun 15, 2023 Pending
Array ( [id] => 19498902 [patent_doc_number] => 20240337920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => DESIGN METHOD OF PHOTOMASK STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/332773 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2365 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332773 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/332773
DESIGN METHOD OF PHOTOMASK STRUCTURE Jun 11, 2023 Pending
Array ( [id] => 19633519 [patent_doc_number] => 20240411968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => MACHINE LEARNING FOR NETLIST DESIGN [patent_app_type] => utility [patent_app_number] => 18/332416 [patent_app_country] => US [patent_app_date] => 2023-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332416 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/332416
MACHINE LEARNING FOR NETLIST DESIGN Jun 8, 2023 Pending
Array ( [id] => 19099983 [patent_doc_number] => 20240119211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => SEMICONDUCTOR DESIGN OPTIMIZATION SYSTEMS AND METHODS OF OPERATION THEREOF [patent_app_type] => utility [patent_app_number] => 18/206278 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5836 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206278 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206278
SEMICONDUCTOR DESIGN OPTIMIZATION SYSTEMS AND METHODS OF OPERATION THEREOF Jun 5, 2023 Pending
Array ( [id] => 18650172 [patent_doc_number] => 20230296004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => POWER SYSTEM FOR HIGH TEMPERATURE APPLICATIONS WITH RECHARGEABLE ENERGY STORAGE [patent_app_type] => utility [patent_app_number] => 18/201380 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23716 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201380 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201380
Power system for high temperature applications with rechargeable energy storage May 23, 2023 Issued
Array ( [id] => 19603700 [patent_doc_number] => 20240394580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => AUTOMATIC QUANTUM CIRCUIT CONTROL SKIPS [patent_app_type] => utility [patent_app_number] => 18/201381 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11897 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201381 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201381
AUTOMATIC QUANTUM CIRCUIT CONTROL SKIPS May 23, 2023 Pending
Array ( [id] => 18630608 [patent_doc_number] => 20230289502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => RECOVERY OF A HIERARCHICAL FUNCTIONAL REPRESENTATION OF AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/197869 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197869 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/197869
Recovery of a hierarchical functional representation of an integrated circuit May 15, 2023 Issued
Array ( [id] => 18773109 [patent_doc_number] => 20230367938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => METHOD FOR COMPREHENSIVE LOW POWER SIMULATION COVERAGE [patent_app_type] => utility [patent_app_number] => 18/315076 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315076 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315076
METHOD FOR COMPREHENSIVE LOW POWER SIMULATION COVERAGE May 9, 2023 Pending
Array ( [id] => 18600636 [patent_doc_number] => 20230275439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => MULTI-CELL BATTERY MANAGEMENT DEVICE [patent_app_type] => utility [patent_app_number] => 18/144932 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18144932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/144932
Multi-cell battery management device May 8, 2023 Issued
Array ( [id] => 19596017 [patent_doc_number] => 12153865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Logic drive based on standard commodity FPGA IC chips [patent_app_type] => utility [patent_app_number] => 18/195324 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 145 [patent_figures_cnt] => 218 [patent_no_of_words] => 144498 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18195324 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/195324
Logic drive based on standard commodity FPGA IC chips May 8, 2023 Issued
Array ( [id] => 19413738 [patent_doc_number] => 12079558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => On-the-fly multi-bit flip flop generation [patent_app_type] => utility [patent_app_number] => 18/144685 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9591 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18144685 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/144685
On-the-fly multi-bit flip flop generation May 7, 2023 Issued
Array ( [id] => 19530575 [patent_doc_number] => 20240354477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => CONSTANT, EQUAL, OR OPPOSITE REGISTERS OR PORTS DETECTION DURING LOGIC SYNTHESIS [patent_app_type] => utility [patent_app_number] => 18/137382 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18137382 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/137382
CONSTANT, EQUAL, OR OPPOSITE REGISTERS OR PORTS DETECTION DURING LOGIC SYNTHESIS Apr 19, 2023 Pending
Array ( [id] => 18554203 [patent_doc_number] => 20230252216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => METHOD AND APPARATUS FOR ELECTROMIGRATION EVALUATION [patent_app_type] => utility [patent_app_number] => 18/302809 [patent_app_country] => US [patent_app_date] => 2023-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302809 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/302809
Method and apparatus for electromigration evaluation Apr 18, 2023 Issued
Array ( [id] => 18711584 [patent_doc_number] => 20230334213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => ANALOG/MIXED-SIGNAL DEFECT SIMULATION AND ANALYSIS METHODOLOGY [patent_app_type] => utility [patent_app_number] => 18/135732 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18135732 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/135732
ANALOG/MIXED-SIGNAL DEFECT SIMULATION AND ANALYSIS METHODOLOGY Apr 16, 2023 Pending
Array ( [id] => 19482520 [patent_doc_number] => 20240330562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => AUTOMATED MULTI-STAGE DESIGN FLOW BASED ON FINAL QUALITY OF RESULT [patent_app_type] => utility [patent_app_number] => 18/192195 [patent_app_country] => US [patent_app_date] => 2023-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7467 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18192195 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/192195
AUTOMATED MULTI-STAGE DESIGN FLOW BASED ON FINAL QUALITY OF RESULT Mar 28, 2023 Pending
Array ( [id] => 18539734 [patent_doc_number] => 20230244842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS [patent_app_type] => utility [patent_app_number] => 18/126125 [patent_app_country] => US [patent_app_date] => 2023-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 191465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 365 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126125 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/126125
LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS Mar 23, 2023 Pending
Array ( [id] => 18695158 [patent_doc_number] => 20230325578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => METHODS OF DETERMINING AN EFFECT OF ELECTRONIC COMPONENT PLACEMENT ACCURACY ON WIRE LOOPS IN A SEMICONDUCTOR PACKAGE, AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/121100 [patent_app_country] => US [patent_app_date] => 2023-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18121100 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/121100
Methods of determining an effect of electronic component placement accuracy on wire loops in a semiconductor package, and related methods Mar 13, 2023 Issued
Array ( [id] => 18487222 [patent_doc_number] => 20230214568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => DETECTION METHOD, SYSTEM, ELECTRONIC EQUIPMENT, AND STORAGE MEDIUM OF PRODUCT TEST DATA [patent_app_type] => utility [patent_app_number] => 18/119844 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18119844 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/119844
DETECTION METHOD, SYSTEM, ELECTRONIC EQUIPMENT, AND STORAGE MEDIUM OF PRODUCT TEST DATA Mar 9, 2023 Issued
Array ( [id] => 18471681 [patent_doc_number] => 20230205967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => THROUGH-SILICON VIA IN INTEGRATED CIRCUIT PACKAGING [patent_app_type] => utility [patent_app_number] => 18/171072 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171072 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/171072
Through-silicon via in integrated circuit packaging Feb 16, 2023 Issued
Array ( [id] => 18847382 [patent_doc_number] => 20230409786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => RECORDING MEDIUM, DESIGN AIDING METHOD, AND INFORMATION PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 18/170777 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170777 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170777
RECORDING MEDIUM, DESIGN AIDING METHOD, AND INFORMATION PROCESSING DEVICE Feb 16, 2023 Abandoned
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