
Eric T. Oberly
Examiner (ID: 5591, Phone: (571)272-6991 , Office: P/2184 )
| Most Active Art Unit | 2184 |
| Art Unit(s) | 2184 |
| Total Applications | 692 |
| Issued Applications | 505 |
| Pending Applications | 44 |
| Abandoned Applications | 152 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20689420
[patent_doc_number] => 12619569
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-05
[patent_title] => IO processing method and apparatus
[patent_app_type] => utility
[patent_app_number] => 18/770598
[patent_app_country] => US
[patent_app_date] => 2024-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 10230
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 266
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770598
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/770598 | IO processing method and apparatus | Jul 10, 2024 | Issued |
Array
(
[id] => 19530128
[patent_doc_number] => 20240354030
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => STORAGE DEVICE SET INCLUDING STORAGE DEVICE AND RECONFIGURABLE LOGIC CHIP, AND STORAGE SYSTEM INCLUDING STORAGE DEVICE SET
[patent_app_type] => utility
[patent_app_number] => 18/760205
[patent_app_country] => US
[patent_app_date] => 2024-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11142
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760205
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/760205 | STORAGE DEVICE SET INCLUDING STORAGE DEVICE AND RECONFIGURABLE LOGIC CHIP, AND STORAGE SYSTEM INCLUDING STORAGE DEVICE SET | Jun 30, 2024 | Pending |
Array
(
[id] => 20395014
[patent_doc_number] => 20250370489
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-04
[patent_title] => POWER DELIVERY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/744706
[patent_app_country] => US
[patent_app_date] => 2024-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744706
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/744706 | POWER DELIVERY SYSTEM | Jun 16, 2024 | Pending |
Array
(
[id] => 20758172
[patent_doc_number] => 12650943
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-09
[patent_title] => Feature management for input/output (I/O) adapters
[patent_app_type] => utility
[patent_app_number] => 18/744032
[patent_app_country] => US
[patent_app_date] => 2024-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3447
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744032
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/744032 | Feature management for input/output (I/O) adapters | Jun 13, 2024 | Issued |
Array
(
[id] => 20159881
[patent_doc_number] => 12386507
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-12
[patent_title] => Creation and use of an efficiency set to estimate an amount of data stored in a data set of a storage system having one or more characteristics
[patent_app_type] => utility
[patent_app_number] => 18/672641
[patent_app_country] => US
[patent_app_date] => 2024-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 7550
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672641
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/672641 | Creation and use of an efficiency set to estimate an amount of data stored in a data set of a storage system having one or more characteristics | May 22, 2024 | Issued |
Array
(
[id] => 20380536
[patent_doc_number] => 20250363029
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-27
[patent_title] => BMC/MULTI-GPU MONITORING/MANAGEMENT SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/672329
[patent_app_country] => US
[patent_app_date] => 2024-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4685
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672329
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/672329 | BMC/multi-GPU monitoring/management system | May 22, 2024 | Issued |
Array
(
[id] => 19603320
[patent_doc_number] => 20240394200
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-28
[patent_title] => HBM OR OTHER TYPE MEMORY WITH FLC SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/669389
[patent_app_country] => US
[patent_app_date] => 2024-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 38429
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669389
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/669389 | HBM OR OTHER TYPE MEMORY WITH FLC SYSTEM | May 19, 2024 | Abandoned |
Array
(
[id] => 20529122
[patent_doc_number] => 12547557
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-10
[patent_title] => System and method for facilitating efficient event notification management for a network interface controller (NIC)
[patent_app_type] => utility
[patent_app_number] => 18/655405
[patent_app_country] => US
[patent_app_date] => 2024-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 1132
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655405
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/655405 | System and method for facilitating efficient event notification management for a network interface controller (NIC) | May 5, 2024 | Issued |
Array
(
[id] => 20249894
[patent_doc_number] => 20250298763
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-25
[patent_title] => MAPPING ABSTRACT DATA MOVEMENTS INTO SEQUENTIAL AND PARALLEL DIRECT MEMORY ACCESS (DMA) PROGRAMMING
[patent_app_type] => utility
[patent_app_number] => 18/631701
[patent_app_country] => US
[patent_app_date] => 2024-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23825
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631701
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/631701 | MAPPING ABSTRACT DATA MOVEMENTS INTO SEQUENTIAL AND PARALLEL DIRECT MEMORY ACCESS (DMA) PROGRAMMING | Apr 9, 2024 | Pending |
Array
(
[id] => 20196401
[patent_doc_number] => 20250273111
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-28
[patent_title] => DISPLAY AND DATA CONFIGURATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/629385
[patent_app_country] => US
[patent_app_date] => 2024-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629385
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/629385 | DISPLAY AND DATA CONFIGURATION METHOD THEREOF | Apr 7, 2024 | Pending |
Array
(
[id] => 20317291
[patent_doc_number] => 12455842
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-28
[patent_title] => Cross address-space bridging
[patent_app_type] => utility
[patent_app_number] => 18/444804
[patent_app_country] => US
[patent_app_date] => 2024-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2210
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444804
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/444804 | Cross address-space bridging | Feb 18, 2024 | Issued |
Array
(
[id] => 20203126
[patent_doc_number] => 12405905
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-02
[patent_title] => Storage device for high speed link startup and storage system including the same
[patent_app_type] => utility
[patent_app_number] => 18/438795
[patent_app_country] => US
[patent_app_date] => 2024-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 13409
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438795
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/438795 | Storage device for high speed link startup and storage system including the same | Feb 11, 2024 | Issued |
Array
(
[id] => 20052168
[patent_doc_number] => 20250190390
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-12
[patent_title] => SYNCHRONIZATION OF STREAMING DATA BETWEEN TWO PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/434221
[patent_app_country] => US
[patent_app_date] => 2024-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7338
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434221
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/434221 | SYNCHRONIZATION OF STREAMING DATA BETWEEN TWO PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) DEVICES | Feb 5, 2024 | Pending |
Array
(
[id] => 20061770
[patent_doc_number] => 20250199992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-19
[patent_title] => ASYNCHRONOUS DOUBLE DATA-LANE DDR (ADL-DDR)
[patent_app_type] => utility
[patent_app_number] => 18/543931
[patent_app_country] => US
[patent_app_date] => 2023-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9519
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18543931
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/543931 | ASYNCHRONOUS DOUBLE DATA-LANE DDR (ADL-DDR) | Dec 17, 2023 | Issued |
Array
(
[id] => 19978797
[patent_doc_number] => 12346272
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-01
[patent_title] => System and method for facilitating on-demand paging in a network interface controller (NIC)
[patent_app_type] => utility
[patent_app_number] => 18/539907
[patent_app_country] => US
[patent_app_date] => 2023-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18539907
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/539907 | System and method for facilitating on-demand paging in a network interface controller (NIC) | Dec 13, 2023 | Issued |
Array
(
[id] => 20043324
[patent_doc_number] => 20250181546
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-05
[patent_title] => Scheduling-Based Idle Power Reduction For Machine Learning Accelerator Systems
[patent_app_type] => utility
[patent_app_number] => 18/527915
[patent_app_country] => US
[patent_app_date] => 2023-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527915
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/527915 | Scheduling-Based Idle Power Reduction For Machine Learning Accelerator Systems | Dec 3, 2023 | Pending |
Array
(
[id] => 19307577
[patent_doc_number] => 20240236158
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-11
[patent_title] => SYSTEM AND METHOD FOR DETERMINING THE STATE OF A TELEVISION
[patent_app_type] => utility
[patent_app_number] => 18/518086
[patent_app_country] => US
[patent_app_date] => 2023-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11233
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -33
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518086
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/518086 | SYSTEM AND METHOD FOR DETERMINING THE STATE OF A TELEVISION | Nov 21, 2023 | Pending |
Array
(
[id] => 20018143
[patent_doc_number] => 20250156365
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-15
[patent_title] => LOW LATENCY GIGABIT PHY-BASED SIGNAL SWITCHING FOR EMULATION, PROTOTYPING, AND HIGH PERFORMANCE COMPUTING
[patent_app_type] => utility
[patent_app_number] => 18/508091
[patent_app_country] => US
[patent_app_date] => 2023-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9772
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18508091
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/508091 | LOW LATENCY GIGABIT PHY-BASED SIGNAL SWITCHING FOR EMULATION, PROTOTYPING, AND HIGH PERFORMANCE COMPUTING | Nov 12, 2023 | Pending |
Array
(
[id] => 20215134
[patent_doc_number] => 12411787
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-09
[patent_title] => Soft disconnect and reconnect for USB tunneled path
[patent_app_type] => utility
[patent_app_number] => 18/502455
[patent_app_country] => US
[patent_app_date] => 2023-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 1233
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18502455
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/502455 | Soft disconnect and reconnect for USB tunneled path | Nov 5, 2023 | Issued |
Array
(
[id] => 20000527
[patent_doc_number] => 20250138749
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-01
[patent_title] => DATA COLLECTION AND STORAGE DURING LOW-POWER STATES
[patent_app_type] => utility
[patent_app_number] => 18/385117
[patent_app_country] => US
[patent_app_date] => 2023-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2329
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18385117
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/385117 | DATA COLLECTION AND STORAGE DURING LOW-POWER STATES | Oct 29, 2023 | Pending |