Search

Erica E. Cadugan

Examiner (ID: 10388, Phone: (571)272-4474 , Office: P/3722 )

Most Active Art Unit
3722
Art Unit(s)
3726, 3722
Total Applications
1811
Issued Applications
1337
Pending Applications
125
Abandoned Applications
364

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9680383 [patent_doc_number] => 08819310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'System-on-chip and data arbitration method thereof' [patent_app_type] => utility [patent_app_number] => 13/276748 [patent_app_country] => US [patent_app_date] => 2011-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6247 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13276748 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/276748
System-on-chip and data arbitration method thereof Oct 18, 2011 Issued
Array ( [id] => 8449074 [patent_doc_number] => 08291141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Mechanism to flexibly support multiple device numbers on point-to-point interconnect upstream ports' [patent_app_type] => utility [patent_app_number] => 13/270073 [patent_app_country] => US [patent_app_date] => 2011-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8005 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13270073 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/270073
Mechanism to flexibly support multiple device numbers on point-to-point interconnect upstream ports Oct 9, 2011 Issued
Array ( [id] => 8354938 [patent_doc_number] => 08250278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Dock-specific display modes' [patent_app_type] => utility [patent_app_number] => 13/250263 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 29965 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13250263 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/250263
Dock-specific display modes Sep 29, 2011 Issued
Array ( [id] => 8378191 [patent_doc_number] => 08260999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Wireless communication with a dock' [patent_app_type] => utility [patent_app_number] => 13/250574 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 34499 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13250574 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/250574
Wireless communication with a dock Sep 29, 2011 Issued
Array ( [id] => 10034424 [patent_doc_number] => 09075743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-07 [patent_title] => 'Managing bandwidth allocation in a processing node using distributed arbitration' [patent_app_type] => utility [patent_app_number] => 13/237749 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8842 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13237749 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/237749
Managing bandwidth allocation in a processing node using distributed arbitration Sep 19, 2011 Issued
Array ( [id] => 8247083 [patent_doc_number] => 08205029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-19 [patent_title] => 'Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)' [patent_app_type] => utility [patent_app_number] => 13/230130 [patent_app_country] => US [patent_app_date] => 2011-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2563 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/205/08205029.pdf [firstpage_image] =>[orig_patent_app_number] => 13230130 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/230130
Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) Sep 11, 2011 Issued
Array ( [id] => 9235875 [patent_doc_number] => 08601191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-03 [patent_title] => 'Bus system and deadlock avoidance circuit thereof' [patent_app_type] => utility [patent_app_number] => 13/137191 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 38 [patent_no_of_words] => 18269 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13137191 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/137191
Bus system and deadlock avoidance circuit thereof Jul 26, 2011 Issued
Array ( [id] => 9404646 [patent_doc_number] => 08694710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'Conversion of a two-wire bus into a single-wire bus' [patent_app_type] => utility [patent_app_number] => 13/189830 [patent_app_country] => US [patent_app_date] => 2011-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5161 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13189830 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/189830
Conversion of a two-wire bus into a single-wire bus Jul 24, 2011 Issued
Array ( [id] => 8998025 [patent_doc_number] => 08521930 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-27 [patent_title] => 'Method and apparatus for scheduling transactions in a host-controlled packet-based bus environment' [patent_app_type] => utility [patent_app_number] => 13/190237 [patent_app_country] => US [patent_app_date] => 2011-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 42587 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13190237 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/190237
Method and apparatus for scheduling transactions in a host-controlled packet-based bus environment Jul 24, 2011 Issued
Array ( [id] => 8479114 [patent_doc_number] => 20120278521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'EMBEDDED SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/189581 [patent_app_country] => US [patent_app_date] => 2011-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1445 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13189581 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/189581
Embedded system capable of decreasing interrupt frequency of arm processor thereof Jul 24, 2011 Issued
Array ( [id] => 7746783 [patent_doc_number] => 20120023278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'EXPANDER TO CONTROL MULTIPATHS IN A STORAGE NETWORK' [patent_app_type] => utility [patent_app_number] => 13/189253 [patent_app_country] => US [patent_app_date] => 2011-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7627 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20120023278.pdf [firstpage_image] =>[orig_patent_app_number] => 13189253 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/189253
EXPANDER TO CONTROL MULTIPATHS IN A STORAGE NETWORK Jul 21, 2011 Abandoned
Array ( [id] => 9102597 [patent_doc_number] => 08566491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'System and method for improving throughput of data transfers using a shared non-deterministic bus' [patent_app_type] => utility [patent_app_number] => 13/186416 [patent_app_country] => US [patent_app_date] => 2011-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 21291 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13186416 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/186416
System and method for improving throughput of data transfers using a shared non-deterministic bus Jul 18, 2011 Issued
Array ( [id] => 8222839 [patent_doc_number] => 20120137038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-31 [patent_title] => 'ELECTRONIC SYSTEMS SUPPORTING MULTIPLE OPERATION MODES AND OPEARATION METHODS THEREOF' [patent_app_type] => utility [patent_app_number] => 13/184345 [patent_app_country] => US [patent_app_date] => 2011-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4674 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13184345 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/184345
ELECTRONIC SYSTEMS SUPPORTING MULTIPLE OPERATION MODES AND OPEARATION METHODS THEREOF Jul 14, 2011 Abandoned
Array ( [id] => 7746781 [patent_doc_number] => 20120023277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'Method for Operating an Automation Device' [patent_app_type] => utility [patent_app_number] => 13/184365 [patent_app_country] => US [patent_app_date] => 2011-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3195 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20120023277.pdf [firstpage_image] =>[orig_patent_app_number] => 13184365 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/184365
Method for Operating an Automation Device Jul 14, 2011 Abandoned
Array ( [id] => 8259943 [patent_doc_number] => 08209456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Integrating non-peripheral component interconnect (PCI) resources into a personal computer system' [patent_app_type] => utility [patent_app_number] => 13/180697 [patent_app_country] => US [patent_app_date] => 2011-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1802 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13180697 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/180697
Integrating non-peripheral component interconnect (PCI) resources into a personal computer system Jul 11, 2011 Issued
Array ( [id] => 8378187 [patent_doc_number] => 08260995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Processor interrupt command response system' [patent_app_type] => utility [patent_app_number] => 13/178050 [patent_app_country] => US [patent_app_date] => 2011-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13178050 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/178050
Processor interrupt command response system Jul 6, 2011 Issued
Array ( [id] => 7493109 [patent_doc_number] => 20110239025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'System and Method for Adapting a Power Usage of a Server During a Data Center Cooling Failure' [patent_app_type] => utility [patent_app_number] => 13/154059 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20110239025.pdf [firstpage_image] =>[orig_patent_app_number] => 13154059 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/154059
System and method for adapting a power usage of a server during a data center cooling failure Jun 5, 2011 Issued
Array ( [id] => 8504442 [patent_doc_number] => 20120303850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'SYSTEMS AND METHODS FOR ADVANCED INTERRUPT SCHEDULING AND PRIORITY PROCESSING IN A STORAGE SYSTEM ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 13/115260 [patent_app_country] => US [patent_app_date] => 2011-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13115260 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/115260
Systems and methods for advanced interrupt scheduling and priority processing in a storage system environment May 24, 2011 Issued
Array ( [id] => 8497699 [patent_doc_number] => 20120297107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-22 [patent_title] => 'STORAGE CONTROLLER SYSTEM WITH DATA SYNCHRONIZATION AND METHOD OF OPERATION THEREOF' [patent_app_type] => utility [patent_app_number] => 13/112988 [patent_app_country] => US [patent_app_date] => 2011-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4573 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13112988 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/112988
Storage controller system with data synchronization and method of operation thereof May 19, 2011 Issued
Array ( [id] => 9218374 [patent_doc_number] => 08631184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Interconnection method and device, for example for systems-on-chip' [patent_app_type] => utility [patent_app_number] => 13/112802 [patent_app_country] => US [patent_app_date] => 2011-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3479 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13112802 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/112802
Interconnection method and device, for example for systems-on-chip May 19, 2011 Issued
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