
Erik T. Peterson
Examiner (ID: 19448, Phone: (571)272-3997 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822, 2898 |
| Total Applications | 486 |
| Issued Applications | 320 |
| Pending Applications | 88 |
| Abandoned Applications | 93 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20583111
[patent_doc_number] => 12575374
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-03-10
[patent_title] => Method of preparing a structured substrate for direct bonding
[patent_app_type] => utility
[patent_app_number] => 19/180420
[patent_app_country] => US
[patent_app_date] => 2025-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 45
[patent_no_of_words] => 1048
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19180420
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/180420 | Method of preparing a structured substrate for direct bonding | Apr 15, 2025 | Issued |
Array
(
[id] => 19662277
[patent_doc_number] => 20240429342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-26
[patent_title] => METHOD FOR SINGULATING A SEMICONDUCTOR COMPONENT HAVING A PN JUNCTION AND SEMICONDUCTOR COMPONENT HAVING A PN JUNCTION
[patent_app_type] => utility
[patent_app_number] => 18/822954
[patent_app_country] => US
[patent_app_date] => 2024-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5769
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 366
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18822954
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/822954 | METHOD FOR SINGULATING A SEMICONDUCTOR COMPONENT HAVING A PN JUNCTION AND SEMICONDUCTOR COMPONENT HAVING A PN JUNCTION | Sep 2, 2024 | Pending |
Array
(
[id] => 19546447
[patent_doc_number] => 20240363483
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/769425
[patent_app_country] => US
[patent_app_date] => 2024-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8618
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769425
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/769425 | SEMICONDUCTOR PACKAGE STRUCTURE | Jul 10, 2024 | Pending |
Array
(
[id] => 19546368
[patent_doc_number] => 20240363404
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => ION IMPLANT PROCESS FOR DEFECT ELIMINATION IN METAL LAYER PLANARIZATION
[patent_app_type] => utility
[patent_app_number] => 18/767722
[patent_app_country] => US
[patent_app_date] => 2024-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6494
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767722
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/767722 | ION IMPLANT PROCESS FOR DEFECT ELIMINATION IN METAL LAYER PLANARIZATION | Jul 8, 2024 | Pending |
Array
(
[id] => 19515775
[patent_doc_number] => 20240347461
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-17
[patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/755686
[patent_app_country] => US
[patent_app_date] => 2024-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4196
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18755686
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/755686 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THEREOF | Jun 26, 2024 | Pending |
Array
(
[id] => 19646538
[patent_doc_number] => 20240421058
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-19
[patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/644867
[patent_app_country] => US
[patent_app_date] => 2024-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8477
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18644867
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/644867 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME | Apr 23, 2024 | Pending |
Array
(
[id] => 19866449
[patent_doc_number] => 20250105235
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-27
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/620416
[patent_app_country] => US
[patent_app_date] => 2024-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12369
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620416
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/620416 | SEMICONDUCTOR PACKAGE | Mar 27, 2024 | Pending |
Array
(
[id] => 19995636
[patent_doc_number] => 20250133858
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-24
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/620999
[patent_app_country] => US
[patent_app_date] => 2024-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1136
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620999
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/620999 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | Mar 27, 2024 | Pending |
Array
(
[id] => 20286194
[patent_doc_number] => 20250311436
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-02
[patent_title] => HYBRID BULK SEMICONDUCTOR AND SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE AND METHODS OF FORMATION
[patent_app_type] => utility
[patent_app_number] => 18/618312
[patent_app_country] => US
[patent_app_date] => 2024-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7749
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618312
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/618312 | HYBRID BULK SEMICONDUCTOR AND SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE AND METHODS OF FORMATION | Mar 26, 2024 | Pending |
Array
(
[id] => 19590092
[patent_doc_number] => 20240387649
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-21
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/613754
[patent_app_country] => US
[patent_app_date] => 2024-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8423
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613754
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/613754 | SEMICONDUCTOR DEVICE | Mar 21, 2024 | Pending |
Array
(
[id] => 19468394
[patent_doc_number] => 20240322064
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => Photodiodes
[patent_app_type] => utility
[patent_app_number] => 18/609426
[patent_app_country] => US
[patent_app_date] => 2024-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3549
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 240
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609426
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/609426 | Photodiodes | Mar 18, 2024 | Pending |
Array
(
[id] => 20223034
[patent_doc_number] => 20250285965
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-11
[patent_title] => PINWHEEL-SHAPED CONNECTIONS BETWEEN DIAGONALLY OPPOSITE INTEGRATED CIRCUITS IN A MULTI-CHIP MODULE TO REDUCE NUMBER OF ROUTING LAYERS
[patent_app_type] => utility
[patent_app_number] => 18/597807
[patent_app_country] => US
[patent_app_date] => 2024-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3280
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18597807
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/597807 | PINWHEEL-SHAPED CONNECTIONS BETWEEN DIAGONALLY OPPOSITE INTEGRATED CIRCUITS IN A MULTI-CHIP MODULE TO REDUCE NUMBER OF ROUTING LAYERS | Mar 5, 2024 | Pending |
Array
(
[id] => 19591824
[patent_doc_number] => 20240389381
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-21
[patent_title] => LIGHT EMITTING ELEMENT
[patent_app_type] => utility
[patent_app_number] => 18/590877
[patent_app_country] => US
[patent_app_date] => 2024-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8345
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18590877
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/590877 | LIGHT EMITTING ELEMENT | Feb 27, 2024 | Pending |
Array
(
[id] => 19221581
[patent_doc_number] => 20240186285
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-06
[patent_title] => PRE-STACKING MECHANICAL STRENGTH ENHANCEMENT OF POWER DEVICE STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 18/444221
[patent_app_country] => US
[patent_app_date] => 2024-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7888
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444221
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/444221 | PRE-STACKING MECHANICAL STRENGTH ENHANCEMENT OF POWER DEVICE STRUCTURES | Feb 15, 2024 | Pending |
Array
(
[id] => 19306074
[patent_doc_number] => 20240234654
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-11
[patent_title] => DISPLAY MODULE AND WEARABLE ELECTRONIC DEVICE INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/444194
[patent_app_country] => US
[patent_app_date] => 2024-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14613
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444194
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/444194 | DISPLAY MODULE AND WEARABLE ELECTRONIC DEVICE INCLUDING THE SAME | Feb 15, 2024 | Pending |
Array
(
[id] => 19790109
[patent_doc_number] => 20250063788
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-20
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/431190
[patent_app_country] => US
[patent_app_date] => 2024-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12695
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18431190
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/431190 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME | Feb 1, 2024 | Pending |
Array
(
[id] => 20141028
[patent_doc_number] => 20250248072
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-31
[patent_title] => SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/425352
[patent_app_country] => US
[patent_app_date] => 2024-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5377
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425352
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/425352 | SEMICONDUCTOR STRUCTURE | Jan 28, 2024 | Pending |
Array
(
[id] => 19191419
[patent_doc_number] => 20240170332
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => WAFER WITH TEST STRUCTURE AND METHOD OF DICING WAFER
[patent_app_type] => utility
[patent_app_number] => 18/420779
[patent_app_country] => US
[patent_app_date] => 2024-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3379
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420779
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/420779 | WAFER WITH TEST STRUCTURE AND METHOD OF DICING WAFER | Jan 23, 2024 | Pending |
Array
(
[id] => 19894811
[patent_doc_number] => 20250120123
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-10
[patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/421144
[patent_app_country] => US
[patent_app_date] => 2024-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9844
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421144
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/421144 | SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME | Jan 23, 2024 | Pending |
Array
(
[id] => 19351471
[patent_doc_number] => 20240260435
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => DISPLAY APPARATUS AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/420341
[patent_app_country] => US
[patent_app_date] => 2024-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5096
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420341
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/420341 | DISPLAY APPARATUS AND METHOD FOR MANUFACTURING THE SAME | Jan 22, 2024 | Pending |