Search

Erik T. Peterson

Examiner (ID: 10756, Phone: (571)272-3997 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2898
Total Applications
454
Issued Applications
306
Pending Applications
78
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13331757 [patent_doc_number] => 20180217416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => TREATING DISPLAY PANEL USING LASER [patent_app_type] => utility [patent_app_number] => 15/419939 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4728 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15419939 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/419939
Treating display panel using laser Jan 29, 2017 Issued
Array ( [id] => 12969124 [patent_doc_number] => 09875948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-23 [patent_title] => Package wafer processing method [patent_app_type] => utility [patent_app_number] => 15/412807 [patent_app_country] => US [patent_app_date] => 2017-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7451 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 526 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15412807 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/412807
Package wafer processing method Jan 22, 2017 Issued
Array ( [id] => 11839994 [patent_doc_number] => 20170221715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'METHOD FOR FORMING JUNCTION IN SEMICONDUCTOR' [patent_app_type] => utility [patent_app_number] => 15/411315 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8545 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411315 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/411315
METHOD FOR FORMING JUNCTION IN SEMICONDUCTOR Jan 19, 2017 Abandoned
Array ( [id] => 15108747 [patent_doc_number] => 10475704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Method of manufacturing element chip and element chip [patent_app_type] => utility [patent_app_number] => 15/408703 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 6590 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408703 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408703
Method of manufacturing element chip and element chip Jan 17, 2017 Issued
Array ( [id] => 11623151 [patent_doc_number] => 20170133338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME' [patent_app_type] => utility [patent_app_number] => 15/405431 [patent_app_country] => US [patent_app_date] => 2017-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5039 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15405431 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/405431
Multilayer pillar for reduced stress interconnect and method of making same Jan 12, 2017 Issued
Array ( [id] => 12896851 [patent_doc_number] => 20180190792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => METHOD OF FORMING SEMICONDUCTOR STRUCTURE AND RESULTING STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/397967 [patent_app_country] => US [patent_app_date] => 2017-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15397967 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/397967
METHOD OF FORMING SEMICONDUCTOR STRUCTURE AND RESULTING STRUCTURE Jan 3, 2017 Abandoned
Array ( [id] => 11557862 [patent_doc_number] => 20170104108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'DOPING AN ABSORBER LAYER OF A PHOTOVOLTAIC DEVICE VIA DIFFUSION FROM A WINDOW LAYER' [patent_app_type] => utility [patent_app_number] => 15/384627 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8946 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15384627 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/384627
DOPING AN ABSORBER LAYER OF A PHOTOVOLTAIC DEVICE VIA DIFFUSION FROM A WINDOW LAYER Dec 19, 2016 Abandoned
Array ( [id] => 13052017 [patent_doc_number] => 10047393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => DNA sequencing using MOSFET transistors [patent_app_type] => utility [patent_app_number] => 15/338734 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4288 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15338734 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/338734
DNA sequencing using MOSFET transistors Oct 30, 2016 Issued
Array ( [id] => 11446207 [patent_doc_number] => 20170047227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'Method of Manufacturing Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 15/335221 [patent_app_country] => US [patent_app_date] => 2016-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 16474 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15335221 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/335221
Method of manufacturing semiconductor device Oct 25, 2016 Issued
Array ( [id] => 11439418 [patent_doc_number] => 20170040439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR FIN STRUCTURE WITH EXTENDING GATE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/298462 [patent_app_country] => US [patent_app_date] => 2016-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5114 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15298462 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/298462
Method for manufacturing semiconductor fin structure with extending gate structure Oct 19, 2016 Issued
Array ( [id] => 11630804 [patent_doc_number] => 20170140993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'GATE STACK INTEGRATED METAL RESISTORS' [patent_app_type] => utility [patent_app_number] => 15/293580 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4347 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15293580 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/293580
Gate stack integrated metal resistors Oct 13, 2016 Issued
Array ( [id] => 14267621 [patent_doc_number] => 10283381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Apparatus for plasma dicing [patent_app_type] => utility [patent_app_number] => 15/293153 [patent_app_country] => US [patent_app_date] => 2016-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3603 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15293153 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/293153
Apparatus for plasma dicing Oct 12, 2016 Issued
Array ( [id] => 11425057 [patent_doc_number] => 20170033203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'MOSFET WITH ULTRA LOW DRAIN LEAKAGE' [patent_app_type] => utility [patent_app_number] => 15/287854 [patent_app_country] => US [patent_app_date] => 2016-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4077 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15287854 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/287854
MOSFET with ultra low drain leakage Oct 6, 2016 Issued
Array ( [id] => 11404773 [patent_doc_number] => 20170025311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-26 [patent_title] => 'Method and Apparatus for Plasma Dicing a Semi-conductor Wafer' [patent_app_type] => utility [patent_app_number] => 15/287412 [patent_app_country] => US [patent_app_date] => 2016-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 19289 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15287412 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/287412
Method and apparatus for plasma dicing a semi-conductor wafer Oct 5, 2016 Issued
Array ( [id] => 11424862 [patent_doc_number] => 20170033008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'Method and Apparatus for Plasma Dicing a Semi-conductor Wafer' [patent_app_type] => utility [patent_app_number] => 15/287501 [patent_app_country] => US [patent_app_date] => 2016-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 19289 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 31 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15287501 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/287501
Method and apparatus for plasma dicing a semi-conductor wafer Oct 5, 2016 Issued
Array ( [id] => 14738547 [patent_doc_number] => 10388684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Image sensor packages formed using temporary protection layers and related methods [patent_app_type] => utility [patent_app_number] => 15/285197 [patent_app_country] => US [patent_app_date] => 2016-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8109 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15285197 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/285197
Image sensor packages formed using temporary protection layers and related methods Oct 3, 2016 Issued
Array ( [id] => 15547447 [patent_doc_number] => 10573513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Semiconductor structures including liners comprising alucone and related methods [patent_app_type] => utility [patent_app_number] => 15/244629 [patent_app_country] => US [patent_app_date] => 2016-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7718 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15244629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/244629
Semiconductor structures including liners comprising alucone and related methods Aug 22, 2016 Issued
Array ( [id] => 11293827 [patent_doc_number] => 20160343759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'PHOTODETECTOR AND METHOD OF FORMING THE PHOTODETECTOR ON STACKED TRENCH ISOLATION REGIONS' [patent_app_type] => utility [patent_app_number] => 15/215674 [patent_app_country] => US [patent_app_date] => 2016-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11593 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15215674 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/215674
Photodetector and method of forming the photodetector on stacked trench isolation regions Jul 20, 2016 Issued
Array ( [id] => 12760114 [patent_doc_number] => 20180145206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/580134 [patent_app_country] => US [patent_app_date] => 2016-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15580134 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/580134
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Jul 3, 2016 Abandoned
Array ( [id] => 11111110 [patent_doc_number] => 20160308080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'SOLAR CELL AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/192037 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7562 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192037 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/192037
SOLAR CELL AND MANUFACTURING METHOD THEREOF Jun 23, 2016 Abandoned
Menu