Search

Erik T. Peterson

Examiner (ID: 11366, Phone: (571)272-3997 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2898, 2822
Total Applications
468
Issued Applications
311
Pending Applications
83
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9016005 [patent_doc_number] => 20130230969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'Method and Apparatus for Plasma Dicing a Semi-conductor Wafer' [patent_app_type] => utility [patent_app_number] => 13/764160 [patent_app_country] => US [patent_app_date] => 2013-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9069 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 34 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13764160 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/764160
Method and apparatus for plasma dicing a semi-conductor wafer Feb 10, 2013 Issued
Array ( [id] => 9597294 [patent_doc_number] => 20140193974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'MULTI-PATTERNING METHOD AND DEVICE FORMED BY THE METHOD' [patent_app_type] => utility [patent_app_number] => 13/737192 [patent_app_country] => US [patent_app_date] => 2013-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13737192 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/737192
Multi-patterning method and device formed by the method Jan 8, 2013 Issued
Array ( [id] => 9588544 [patent_doc_number] => 08778081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Process and hardware for deposition of complex thin-film alloys over large areas' [patent_app_type] => utility [patent_app_number] => 13/733716 [patent_app_country] => US [patent_app_date] => 2013-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 14503 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13733716 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/733716
Process and hardware for deposition of complex thin-film alloys over large areas Jan 2, 2013 Issued
Array ( [id] => 10888027 [patent_doc_number] => 08912022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Methods for making light emitting diodes and optical elements' [patent_app_type] => utility [patent_app_number] => 13/728076 [patent_app_country] => US [patent_app_date] => 2012-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5817 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13728076 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/728076
Methods for making light emitting diodes and optical elements Dec 26, 2012 Issued
Array ( [id] => 9569282 [patent_doc_number] => 20140186995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'Method of fabricating cigs solar cells with high band gap by sequential processing' [patent_app_type] => utility [patent_app_number] => 13/727883 [patent_app_country] => US [patent_app_date] => 2012-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 18473 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13727883 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/727883
Method of fabricating cigs solar cells with high band gap by sequential processing Dec 26, 2012 Abandoned
Array ( [id] => 9127025 [patent_doc_number] => 08574974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/721228 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 35 [patent_no_of_words] => 5878 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 788 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721228 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/721228
Method of manufacturing a semiconductor device Dec 19, 2012 Issued
Array ( [id] => 9561370 [patent_doc_number] => 20140179083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'HIGH DIE STRENGTH SEMICONDUCTOR WAFER PROCESSING METHOD AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/721674 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5218 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721674 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/721674
High die strength semiconductor wafer processing method and system Dec 19, 2012 Issued
Array ( [id] => 8891711 [patent_doc_number] => 20130164895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'Trench-Gated Power Devices with Two Types of Trenches and Reliable Polycidation' [patent_app_type] => utility [patent_app_number] => 13/709281 [patent_app_country] => US [patent_app_date] => 2012-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7094 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13709281 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/709281
Trench-Gated Power Devices with Two Types of Trenches and Reliable Polycidation Dec 9, 2012 Abandoned
Array ( [id] => 9491199 [patent_doc_number] => 20140141605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'FINFET FORMATION USING DOUBLE PATTERNING MEMORIZATION' [patent_app_type] => utility [patent_app_number] => 13/682769 [patent_app_country] => US [patent_app_date] => 2012-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13682769 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/682769
FinFET formation using double patterning memorization Nov 20, 2012 Issued
Array ( [id] => 8825831 [patent_doc_number] => 20130126876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'ARRAY SUBSTRATE FOR FRINGE FIELD SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/679643 [patent_app_country] => US [patent_app_date] => 2012-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6479 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13679643 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/679643
Array substrate for fringe field switching mode liquid crystal display device and method for fabricating the same Nov 15, 2012 Issued
Array ( [id] => 9449520 [patent_doc_number] => 20140120690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'Streamlined Process for Vertical Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 13/666193 [patent_app_country] => US [patent_app_date] => 2012-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3278 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13666193 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/666193
Streamlined process for vertical semiconductor devices Oct 31, 2012 Issued
Array ( [id] => 8916424 [patent_doc_number] => 20130178049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'METHOD OF MANUFACTURING SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/656734 [patent_app_country] => US [patent_app_date] => 2012-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5903 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13656734 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/656734
Method of manufacturing substrate Oct 20, 2012 Issued
Array ( [id] => 11911369 [patent_doc_number] => 09780190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'InP-based transistor fabrication' [patent_app_type] => utility [patent_app_number] => 13/654531 [patent_app_country] => US [patent_app_date] => 2012-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 10499 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13654531 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/654531
InP-based transistor fabrication Oct 17, 2012 Issued
Array ( [id] => 9869212 [patent_doc_number] => 08956984 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Method of manufacturing semiconductor device, method of processing substrate, substrate processing apparatus, and non-transitory computer-readable recording medium' [patent_app_type] => utility [patent_app_number] => 13/647908 [patent_app_country] => US [patent_app_date] => 2012-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 31 [patent_no_of_words] => 36472 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13647908 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/647908
Method of manufacturing semiconductor device, method of processing substrate, substrate processing apparatus, and non-transitory computer-readable recording medium Oct 8, 2012 Issued
Array ( [id] => 9408533 [patent_doc_number] => 20140099785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'Sacrificial Low Work Function Cap Layer' [patent_app_type] => utility [patent_app_number] => 13/645259 [patent_app_country] => US [patent_app_date] => 2012-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4504 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13645259 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/645259
Sacrificial Low Work Function Cap Layer Oct 3, 2012 Abandoned
Array ( [id] => 8916395 [patent_doc_number] => 20130178020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'FINFET WITH FULLY SILICIDED GATE' [patent_app_type] => utility [patent_app_number] => 13/614662 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3157 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13614662 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/614662
finFET with fully silicided gate Sep 12, 2012 Issued
Array ( [id] => 9468861 [patent_doc_number] => 08722491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'Replacement metal gate semiconductor device formation using low resistivity metals' [patent_app_type] => utility [patent_app_number] => 13/603726 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 3234 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13603726 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/603726
Replacement metal gate semiconductor device formation using low resistivity metals Sep 4, 2012 Issued
Array ( [id] => 10518875 [patent_doc_number] => 09245930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Method of manufacturing display panel' [patent_app_type] => utility [patent_app_number] => 14/131788 [patent_app_country] => US [patent_app_date] => 2012-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 13791 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14131788 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/131788
Method of manufacturing display panel Aug 29, 2012 Issued
Array ( [id] => 9330675 [patent_doc_number] => 20140057457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'Non-melt thin-wafer laser thermal annealing methods' [patent_app_type] => utility [patent_app_number] => 13/595873 [patent_app_country] => US [patent_app_date] => 2012-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6571 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13595873 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/595873
Non-melt thin-wafer laser thermal annealing methods Aug 26, 2012 Issued
Array ( [id] => 9455118 [patent_doc_number] => 08716125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Methods of in-situ vapor phase deposition of self-assembled monolayers as copper adhesion promoters and diffusion barriers' [patent_app_type] => utility [patent_app_number] => 13/571470 [patent_app_country] => US [patent_app_date] => 2012-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2846 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13571470 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/571470
Methods of in-situ vapor phase deposition of self-assembled monolayers as copper adhesion promoters and diffusion barriers Aug 9, 2012 Issued
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