
Erik T. Peterson
Examiner (ID: 11366, Phone: (571)272-3997 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2898, 2822 |
| Total Applications | 468 |
| Issued Applications | 311 |
| Pending Applications | 83 |
| Abandoned Applications | 93 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8379704
[patent_doc_number] => 20120223331
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-09-06
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/063745
[patent_app_country] => US
[patent_app_date] => 2011-03-02
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13063745
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/063745 | Semiconductor device and method for forming the same | Mar 1, 2011 | Issued |
Array
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[patent_doc_number] => 08896062
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[patent_kind] => B2
[patent_issue_date] => 2014-11-25
[patent_title] => 'Semiconductor device and method for forming the same'
[patent_app_type] => utility
[patent_app_number] => 13/143931
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13143931
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/143931 | Semiconductor device and method for forming the same | Feb 23, 2011 | Issued |
Array
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[id] => 7751372
[patent_doc_number] => 20120025862
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-02-02
[patent_title] => 'Test Structure for ILD Void Testing and Conduct Resistance Measurement in a Semiconductor Device'
[patent_app_type] => utility
[patent_app_number] => 13/020127
[patent_app_country] => US
[patent_app_date] => 2011-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => publications/A1/0025/20120025862.pdf
[firstpage_image] =>[orig_patent_app_number] => 13020127
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/020127 | Test structure for ILD void testing and contact resistance measurement in a semiconductor device | Feb 2, 2011 | Issued |
Array
(
[id] => 8483308
[patent_doc_number] => 20120282715
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-08
[patent_title] => 'STRUCTURE MANUFACTURING METHOD AND LIQUID DISCHARGE HEAD SUBSTRATE MANUFACTURING METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/521694
[patent_app_country] => US
[patent_app_date] => 2011-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/521694 | Structure manufacturing method and liquid discharge head substrate manufacturing method | Jan 12, 2011 | Issued |
Array
(
[id] => 8566613
[patent_doc_number] => 20120329184
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-12-27
[patent_title] => 'CASTING COMPOSITION AS DIFFUSION BARRIER FOR WATER MOLECULES'
[patent_app_type] => utility
[patent_app_number] => 13/519945
[patent_app_country] => US
[patent_app_date] => 2010-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13519945
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/519945 | Casting composition as diffusion barrier for water molecules | Nov 30, 2010 | Issued |
Array
(
[id] => 8495971
[patent_doc_number] => 20120295379
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-22
[patent_title] => 'DEPOSITION MASK, DEPOSITION APPARATUS, AND DEPOSITION METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/522007
[patent_app_country] => US
[patent_app_date] => 2010-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13522007
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/522007 | Deposition apparatus, and deposition method | Oct 28, 2010 | Issued |
Array
(
[id] => 10638440
[patent_doc_number] => 09355951
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[patent_issue_date] => 2016-05-31
[patent_title] => 'Interconnect layouts for electronic assemblies'
[patent_app_type] => utility
[patent_app_number] => 12/855598
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[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12855598
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/855598 | Interconnect layouts for electronic assemblies | Aug 11, 2010 | Issued |
Array
(
[id] => 8252514
[patent_doc_number] => 20120156836
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-21
[patent_title] => 'METHOD FOR FORMING III-V SEMICONDUCTOR STRUCTURES INCLUDING ALUMINUM-SILICON NITRIDE PASSIVATION'
[patent_app_type] => utility
[patent_app_number] => 13/380150
[patent_app_country] => US
[patent_app_date] => 2010-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[pdf_file] => publications/A1/0156/20120156836.pdf
[firstpage_image] =>[orig_patent_app_number] => 13380150
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/380150 | Method for forming III-V semiconductor structures including aluminum-silicon nitride passivation | Jun 27, 2010 | Issued |
Array
(
[id] => 8519777
[patent_doc_number] => 20120319185
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-12-20
[patent_title] => 'NAND STRUCTURE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/063653 | NAND STRUCTURE AND METHOD OF MANUFACTURING THE SAME | Jun 24, 2010 | Abandoned |
Array
(
[id] => 9154080
[patent_doc_number] => 08586987
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-11-19
[patent_title] => 'Active matrix substrate and active matrix display device'
[patent_app_type] => utility
[patent_app_number] => 13/394621
[patent_app_country] => US
[patent_app_date] => 2010-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13394621
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/394621 | Active matrix substrate and active matrix display device | May 20, 2010 | Issued |