Search

Erik T. Peterson

Examiner (ID: 10756, Phone: (571)272-3997 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2898
Total Applications
454
Issued Applications
306
Pending Applications
78
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13349993 [patent_doc_number] => 20180226536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT [patent_app_type] => utility [patent_app_number] => 15/888627 [patent_app_country] => US [patent_app_date] => 2018-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15888627 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/888627
Method of manufacturing nitride semiconductor light-emitting element Feb 4, 2018 Issued
Array ( [id] => 18016293 [patent_doc_number] => 11508599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Pick-up device and pick-up method [patent_app_type] => utility [patent_app_number] => 16/497452 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4010 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16497452 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/497452
Pick-up device and pick-up method Jan 29, 2018 Issued
Array ( [id] => 16280348 [patent_doc_number] => 10763390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Optical device wafer processing method [patent_app_type] => utility [patent_app_number] => 15/876423 [patent_app_country] => US [patent_app_date] => 2018-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5950 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15876423 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/876423
Optical device wafer processing method Jan 21, 2018 Issued
Array ( [id] => 12823588 [patent_doc_number] => 20180166368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => LEAD FRAME [patent_app_type] => utility [patent_app_number] => 15/836044 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15836044 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/836044
Lead frame Dec 7, 2017 Issued
Array ( [id] => 12615540 [patent_doc_number] => 20180097010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/815004 [patent_app_country] => US [patent_app_date] => 2017-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15815004 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/815004
Semiconductor device and method of manufacturing the same Nov 15, 2017 Issued
Array ( [id] => 12162490 [patent_doc_number] => 20180033756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'METHOD FOR FORMING BUMP STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/725535 [patent_app_country] => US [patent_app_date] => 2017-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15725535 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/725535
METHOD FOR FORMING BUMP STRUCTURE Oct 4, 2017 Pending
Array ( [id] => 14920719 [patent_doc_number] => 10431687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Structure and formation method of semiconductor device structure [patent_app_type] => utility [patent_app_number] => 15/687723 [patent_app_country] => US [patent_app_date] => 2017-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687723 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687723
Structure and formation method of semiconductor device structure Aug 27, 2017 Issued
Array ( [id] => 13695329 [patent_doc_number] => 20170358619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => PHOTODETECTOR AND METHOD OF FORMING THE PHOTODETECTOR ON STACKED TRENCH ISOLATION REGIONS [patent_app_type] => utility [patent_app_number] => 15/671223 [patent_app_country] => US [patent_app_date] => 2017-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15671223 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/671223
Photodetector and method of forming the photodetector on stacked trench isolation regions Aug 7, 2017 Issued
Array ( [id] => 13667741 [patent_doc_number] => 10164052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/667629 [patent_app_country] => US [patent_app_date] => 2017-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2043 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15667629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/667629
Semiconductor device and method for fabricating the same Aug 2, 2017 Issued
Array ( [id] => 11869465 [patent_doc_number] => 20170236750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'Method for Via Plating with Seed Layer' [patent_app_type] => utility [patent_app_number] => 15/584981 [patent_app_country] => US [patent_app_date] => 2017-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15584981 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/584981
Method for Via Plating with Seed Layer May 1, 2017 Abandoned
Array ( [id] => 11939770 [patent_doc_number] => 20170243921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'METHODS OF FORMING VERTICAL FIELD-EFFECT TRANSISTOR WITH SELFALIGNED CONTACTS FOR MEMORY DEVICES WITH PLANAR PERIPHERY/ARRAY AND INTERMEDIATE STRUCTURES FORMED THEREBY' [patent_app_type] => utility [patent_app_number] => 15/497032 [patent_app_country] => US [patent_app_date] => 2017-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 7002 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15497032 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/497032
Methods of forming vertical field-effect transistor with selfaligned contacts for memory devices with planar periphery/array and intermediate structures formed thereby Apr 24, 2017 Issued
Array ( [id] => 13667717 [patent_doc_number] => 10164040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Gate structure and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/464698 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 7061 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15464698 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/464698
Gate structure and method for fabricating the same Mar 20, 2017 Issued
Array ( [id] => 11710461 [patent_doc_number] => 20170178960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'SELECTIVE REMOVAL OF SEMICONDUCTOR FINS' [patent_app_type] => utility [patent_app_number] => 15/450829 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 10720 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450829 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450829
Selective removal of semiconductor fins Mar 5, 2017 Issued
Array ( [id] => 11694418 [patent_doc_number] => 20170170135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME' [patent_app_type] => utility [patent_app_number] => 15/445058 [patent_app_country] => US [patent_app_date] => 2017-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5039 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15445058 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/445058
Multilayer pillar for reduced stress interconnect and method of making same Feb 27, 2017 Issued
Array ( [id] => 13748521 [patent_doc_number] => 10167190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Low cost wafer level process for packaging MEMS three dimensional devices [patent_app_type] => utility [patent_app_number] => 15/432880 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 4785 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432880 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/432880
Low cost wafer level process for packaging MEMS three dimensional devices Feb 13, 2017 Issued
Array ( [id] => 12061888 [patent_doc_number] => 20170338232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/432697 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432697 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/432697
METHOD OF FABRICATING SEMICONDUCTOR DEVICE Feb 13, 2017 Abandoned
Array ( [id] => 12849250 [patent_doc_number] => 20180174923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => METHODS FOR FABRICATING METAL GATE STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/429188 [patent_app_country] => US [patent_app_date] => 2017-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15429188 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/429188
Methods for fabricating metal gate structures Feb 9, 2017 Issued
Array ( [id] => 11974695 [patent_doc_number] => 20170278849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/430413 [patent_app_country] => US [patent_app_date] => 2017-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9265 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15430413 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/430413
Method for manufacturing semiconductor device Feb 9, 2017 Issued
Array ( [id] => 13293167 [patent_doc_number] => 10157784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Integration of a self-forming barrier layer and a ruthenium metal liner in copper metallization [patent_app_type] => utility [patent_app_number] => 15/428749 [patent_app_country] => US [patent_app_date] => 2017-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 4237 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15428749 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/428749
Integration of a self-forming barrier layer and a ruthenium metal liner in copper metallization Feb 8, 2017 Issued
Array ( [id] => 13653325 [patent_doc_number] => 09852983 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-26 [patent_title] => Fabricating method of anti-fuse structure [patent_app_type] => utility [patent_app_number] => 15/428137 [patent_app_country] => US [patent_app_date] => 2017-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2537 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15428137 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/428137
Fabricating method of anti-fuse structure Feb 7, 2017 Issued
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