Search

Erma C. Cameron

Examiner (ID: 5420, Phone: (571)272-1416 , Office: P/1715 )

Most Active Art Unit
1762
Art Unit(s)
1112, 1715, 1762, 1773, 1792
Total Applications
2111
Issued Applications
1606
Pending Applications
97
Abandoned Applications
408

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3999521 [patent_doc_number] => 05950089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Method of making read-only memory device having a silicon-on-insulator structure' [patent_app_type] => 1 [patent_app_number] => 8/847521 [patent_app_country] => US [patent_app_date] => 1997-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3899 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 404 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/950/05950089.pdf [firstpage_image] =>[orig_patent_app_number] => 847521 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/847521
Method of making read-only memory device having a silicon-on-insulator structure Apr 21, 1997 Issued
Array ( [id] => 3858647 [patent_doc_number] => 05792684 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Process for fabricating MOS memory devices, with a self-aligned contact structure, and MOS logic devices with salicide, both on a single semiconductor chip' [patent_app_type] => 1 [patent_app_number] => 8/844630 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3143 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 762 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792684.pdf [firstpage_image] =>[orig_patent_app_number] => 844630 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/844630
Process for fabricating MOS memory devices, with a self-aligned contact structure, and MOS logic devices with salicide, both on a single semiconductor chip Apr 20, 1997 Issued
Array ( [id] => 3759659 [patent_doc_number] => 05843823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Method for fabricating a multi-stage ROM structure' [patent_app_type] => 1 [patent_app_number] => 8/844521 [patent_app_country] => US [patent_app_date] => 1997-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 3386 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 506 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/843/05843823.pdf [firstpage_image] =>[orig_patent_app_number] => 844521 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/844521
Method for fabricating a multi-stage ROM structure Apr 17, 1997 Issued
Array ( [id] => 4057157 [patent_doc_number] => 05895242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Read-only memories and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/839633 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 3359 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 450 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895242.pdf [firstpage_image] =>[orig_patent_app_number] => 839633 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839633
Read-only memories and method for manufacturing the same Apr 14, 1997 Issued
Array ( [id] => 4069853 [patent_doc_number] => 05933735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Semiconductor read-only memory device and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 8/839629 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4139 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933735.pdf [firstpage_image] =>[orig_patent_app_number] => 839629 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839629
Semiconductor read-only memory device and method of fabricating the same Apr 14, 1997 Issued
Array ( [id] => 4062779 [patent_doc_number] => 05866457 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Semiconductor read-only memory device and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 8/843343 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3882 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/866/05866457.pdf [firstpage_image] =>[orig_patent_app_number] => 843343 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/843343
Semiconductor read-only memory device and method of fabricating the same Apr 14, 1997 Issued
Array ( [id] => 3877397 [patent_doc_number] => 05804490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Method of filling shallow trenches' [patent_app_type] => 1 [patent_app_number] => 8/824703 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1833 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 399 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/804/05804490.pdf [firstpage_image] =>[orig_patent_app_number] => 824703 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/824703
Method of filling shallow trenches Apr 13, 1997 Issued
Array ( [id] => 3858715 [patent_doc_number] => 05792689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method for manufacturing double-crown capacitors self-aligned to node contacts on dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 8/827817 [patent_app_country] => US [patent_app_date] => 1997-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4990 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792689.pdf [firstpage_image] =>[orig_patent_app_number] => 827817 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/827817
Method for manufacturing double-crown capacitors self-aligned to node contacts on dynamic random access memory Apr 10, 1997 Issued
Array ( [id] => 3858633 [patent_doc_number] => 05792683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method for manufacturing of an SRAM device' [patent_app_type] => 1 [patent_app_number] => 8/837335 [patent_app_country] => US [patent_app_date] => 1997-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 6815 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792683.pdf [firstpage_image] =>[orig_patent_app_number] => 837335 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/837335
Method for manufacturing of an SRAM device Apr 10, 1997 Issued
Array ( [id] => 4218813 [patent_doc_number] => 06040212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Methods of forming trench-gate semiconductor devices using sidewall implantation techniques to control threshold voltage' [patent_app_type] => 1 [patent_app_number] => 8/833403 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3225 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040212.pdf [firstpage_image] =>[orig_patent_app_number] => 833403 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/833403
Methods of forming trench-gate semiconductor devices using sidewall implantation techniques to control threshold voltage Apr 3, 1997 Issued
Array ( [id] => 4084492 [patent_doc_number] => 06025224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Device with asymmetrical channel dopant profile' [patent_app_type] => 1 [patent_app_number] => 8/829371 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6334 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025224.pdf [firstpage_image] =>[orig_patent_app_number] => 829371 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829371
Device with asymmetrical channel dopant profile Mar 30, 1997 Issued
Array ( [id] => 4206214 [patent_doc_number] => 06027947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Partially or completely encapsulated top electrode of a ferroelectric capacitor' [patent_app_type] => 1 [patent_app_number] => 8/828157 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 89 [patent_no_of_words] => 10313 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/027/06027947.pdf [firstpage_image] =>[orig_patent_app_number] => 828157 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/828157
Partially or completely encapsulated top electrode of a ferroelectric capacitor Mar 26, 1997 Issued
Array ( [id] => 4012149 [patent_doc_number] => 05879985 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Crown capacitor using a tapered etch of a damascene lower electrode' [patent_app_type] => 1 [patent_app_number] => 8/827339 [patent_app_country] => US [patent_app_date] => 1997-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4178 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/879/05879985.pdf [firstpage_image] =>[orig_patent_app_number] => 827339 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/827339
Crown capacitor using a tapered etch of a damascene lower electrode Mar 25, 1997 Issued
Array ( [id] => 4063783 [patent_doc_number] => 06008083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Precision analog metal-metal capacitor' [patent_app_type] => 1 [patent_app_number] => 8/820930 [patent_app_country] => US [patent_app_date] => 1997-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 5414 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008083.pdf [firstpage_image] =>[orig_patent_app_number] => 820930 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/820930
Precision analog metal-metal capacitor Mar 18, 1997 Issued
Array ( [id] => 4009186 [patent_doc_number] => 05920771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Method of making antifuse based on silicided single polysilicon bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/820475 [patent_app_country] => US [patent_app_date] => 1997-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2759 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920771.pdf [firstpage_image] =>[orig_patent_app_number] => 820475 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/820475
Method of making antifuse based on silicided single polysilicon bipolar transistor Mar 16, 1997 Issued
Array ( [id] => 3740520 [patent_doc_number] => 05786250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Method of making a capacitor' [patent_app_type] => 1 [patent_app_number] => 8/818597 [patent_app_country] => US [patent_app_date] => 1997-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5275 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/786/05786250.pdf [firstpage_image] =>[orig_patent_app_number] => 818597 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/818597
Method of making a capacitor Mar 13, 1997 Issued
Array ( [id] => 3941502 [patent_doc_number] => 05989956 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'DRAM capacitor process' [patent_app_type] => 1 [patent_app_number] => 8/814377 [patent_app_country] => US [patent_app_date] => 1997-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3533 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989956.pdf [firstpage_image] =>[orig_patent_app_number] => 814377 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/814377
DRAM capacitor process Mar 10, 1997 Issued
Array ( [id] => 3858772 [patent_doc_number] => 05792693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method for producing capacitors having increased surface area for dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 8/813721 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4862 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 379 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792693.pdf [firstpage_image] =>[orig_patent_app_number] => 813721 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/813721
Method for producing capacitors having increased surface area for dynamic random access memory Mar 6, 1997 Issued
Array ( [id] => 3773949 [patent_doc_number] => 05817554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Use of a grated top surface topography for capacitor structures' [patent_app_type] => 1 [patent_app_number] => 8/813723 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3391 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 437 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/817/05817554.pdf [firstpage_image] =>[orig_patent_app_number] => 813723 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/813723
Use of a grated top surface topography for capacitor structures Mar 6, 1997 Issued
Array ( [id] => 3791452 [patent_doc_number] => 05780332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Method of manufacturing a semiconductor memory device with a trench capacitor' [patent_app_type] => 1 [patent_app_number] => 8/812973 [patent_app_country] => US [patent_app_date] => 1997-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 62 [patent_no_of_words] => 8980 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/780/05780332.pdf [firstpage_image] =>[orig_patent_app_number] => 812973 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/812973
Method of manufacturing a semiconductor memory device with a trench capacitor Mar 4, 1997 Issued
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