
Ermias T. Woldegeorgis
Examiner (ID: 9205, Phone: (571)270-5350 , Office: P/2893 )
| Most Active Art Unit | 2893 |
| Art Unit(s) | 2893, 2821 |
| Total Applications | 990 |
| Issued Applications | 699 |
| Pending Applications | 103 |
| Abandoned Applications | 225 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13543427
[patent_doc_number] => 20180323260
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-08
[patent_title] => DUAL THRESHOLD VOLTAGE (VT) CHANNEL DEVICES AND THEIR METHODS OF FABRICATION
[patent_app_type] => utility
[patent_app_number] => 15/773536
[patent_app_country] => US
[patent_app_date] => 2015-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7252
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15773536
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/773536 | Dual threshold voltage (VT) channel devices and their methods of fabrication | Dec 22, 2015 | Issued |
Array
(
[id] => 13543255
[patent_doc_number] => 20180323174
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-08
[patent_title] => FABRICATION AND USE OF THROUGH SILICON VIAS ON DOUBLE SIDED INTERCONNECT DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/773514
[patent_app_country] => US
[patent_app_date] => 2015-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8480
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15773514
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/773514 | Fabrication and use of through silicon vias on double sided interconnect device | Dec 22, 2015 | Issued |
Array
(
[id] => 11201084
[patent_doc_number] => 09431305
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-08-30
[patent_title] => 'Vertical transistor fabrication and devices'
[patent_app_type] => utility
[patent_app_number] => 14/975168
[patent_app_country] => US
[patent_app_date] => 2015-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 53
[patent_no_of_words] => 15420
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14975168
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/975168 | Vertical transistor fabrication and devices | Dec 17, 2015 | Issued |
Array
(
[id] => 11694301
[patent_doc_number] => 20170170018
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-15
[patent_title] => 'CONFORMAL DOPING USING DOPANT GAS ON HYDROGEN PLASMA TREATED SURFACE'
[patent_app_type] => utility
[patent_app_number] => 14/967994
[patent_app_country] => US
[patent_app_date] => 2015-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6905
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967994
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/967994 | CONFORMAL DOPING USING DOPANT GAS ON HYDROGEN PLASMA TREATED SURFACE | Dec 13, 2015 | Abandoned |
Array
(
[id] => 11246595
[patent_doc_number] => 09472646
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-10-18
[patent_title] => 'Dual work function buried gate type transistor and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 14/965325
[patent_app_country] => US
[patent_app_date] => 2015-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 26
[patent_no_of_words] => 8251
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14965325
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/965325 | Dual work function buried gate type transistor and method for fabricating the same | Dec 9, 2015 | Issued |
Array
(
[id] => 13542895
[patent_doc_number] => 20180322994
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-08
[patent_title] => THERMAL BUDGET ENHANCEMENT OF A MAGNETIC TUNNEL JUNCTION
[patent_app_type] => utility
[patent_app_number] => 15/773339
[patent_app_country] => US
[patent_app_date] => 2015-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6327
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 38
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15773339
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/773339 | THERMAL BUDGET ENHANCEMENT OF A MAGNETIC TUNNEL JUNCTION | Dec 6, 2015 | Abandoned |
Array
(
[id] => 13543297
[patent_doc_number] => 20180323195
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-08
[patent_title] => STACKED CHANNEL STRUCTURES FOR MOSFETS
[patent_app_type] => utility
[patent_app_number] => 15/773325
[patent_app_country] => US
[patent_app_date] => 2015-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23101
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15773325
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/773325 | Stacked channel structures for MOSFETs | Dec 2, 2015 | Issued |
Array
(
[id] => 16218471
[patent_doc_number] => 10734293
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-04
[patent_title] => Process control techniques for semiconductor manufacturing processes
[patent_app_type] => utility
[patent_app_number] => 15/604240
[patent_app_country] => US
[patent_app_date] => 2015-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 14346
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15604240
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/604240 | Process control techniques for semiconductor manufacturing processes | Nov 24, 2015 | Issued |
Array
(
[id] => 13950869
[patent_doc_number] => 10211213
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-19
[patent_title] => Semiconductor device and a manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 14/948339
[patent_app_country] => US
[patent_app_date] => 2015-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 53
[patent_no_of_words] => 30746
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 408
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14948339
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/948339 | Semiconductor device and a manufacturing method thereof | Nov 21, 2015 | Issued |
Array
(
[id] => 11652949
[patent_doc_number] => 20170148849
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-25
[patent_title] => 'SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/948046
[patent_app_country] => US
[patent_app_date] => 2015-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 7040
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14948046
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/948046 | Semiconductor structure and method of forming the same | Nov 19, 2015 | Issued |
Array
(
[id] => 11601535
[patent_doc_number] => 09648729
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-05-09
[patent_title] => 'Stress reduction interposer for ceramic no-lead surface mount electronic device'
[patent_app_type] => utility
[patent_app_number] => 14/947574
[patent_app_country] => US
[patent_app_date] => 2015-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 3603
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14947574
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/947574 | Stress reduction interposer for ceramic no-lead surface mount electronic device | Nov 19, 2015 | Issued |
Array
(
[id] => 10809640
[patent_doc_number] => 20160155798
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-02
[patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE, AND ELECTRONIC DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/947632
[patent_app_country] => US
[patent_app_date] => 2015-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7966
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14947632
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/947632 | Method for manufacturing a semiconductor structure, semiconductor structure, and electronic device | Nov 19, 2015 | Issued |
Array
(
[id] => 11404823
[patent_doc_number] => 20170025361
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-26
[patent_title] => 'SELF SHIELDED SYSTEM IN PACKAGE (SiP) MODULES'
[patent_app_type] => utility
[patent_app_number] => 14/947353
[patent_app_country] => US
[patent_app_date] => 2015-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4903
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14947353
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/947353 | Self shielded system in package (SiP) modules | Nov 19, 2015 | Issued |
Array
(
[id] => 11483476
[patent_doc_number] => 09590033
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-03-07
[patent_title] => 'Trench separation diffusion for high voltage device'
[patent_app_type] => utility
[patent_app_number] => 14/948156
[patent_app_country] => US
[patent_app_date] => 2015-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 4718
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14948156
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/948156 | Trench separation diffusion for high voltage device | Nov 19, 2015 | Issued |
Array
(
[id] => 11652727
[patent_doc_number] => 20170148629
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-25
[patent_title] => 'SILICON-ON-INSULATOR FIN FIELD-EFFECT TRANSISTOR DEVICE FORMED ON A BULK SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 14/947313
[patent_app_country] => US
[patent_app_date] => 2015-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4031
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14947313
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/947313 | Silicon-on-insulator fin field-effect transistor device formed on a bulk substrate | Nov 19, 2015 | Issued |
Array
(
[id] => 10802762
[patent_doc_number] => 20160148919
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-26
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/943103
[patent_app_country] => US
[patent_app_date] => 2015-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 10207
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14943103
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/943103 | Semiconductor device | Nov 16, 2015 | Issued |
Array
(
[id] => 10800748
[patent_doc_number] => 20160146906
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-26
[patent_title] => 'VERTICAL HALL ELEMENT'
[patent_app_type] => utility
[patent_app_number] => 14/943493
[patent_app_country] => US
[patent_app_date] => 2015-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 5217
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14943493
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/943493 | Vertical hall element | Nov 16, 2015 | Issued |
Array
(
[id] => 12416676
[patent_doc_number] => 09972505
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-15
[patent_title] => Semiconductor device and its manufacturing method
[patent_app_type] => utility
[patent_app_number] => 14/943900
[patent_app_country] => US
[patent_app_date] => 2015-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 14623
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14943900
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/943900 | Semiconductor device and its manufacturing method | Nov 16, 2015 | Issued |
Array
(
[id] => 10802875
[patent_doc_number] => 20160149032
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-26
[patent_title] => 'Power Transistor with Field-Electrode'
[patent_app_type] => utility
[patent_app_number] => 14/943524
[patent_app_country] => US
[patent_app_date] => 2015-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6899
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14943524
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/943524 | Power Transistor with Field-Electrode | Nov 16, 2015 | Abandoned |
Array
(
[id] => 11321722
[patent_doc_number] => 09520471
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-12-13
[patent_title] => 'Semiconductor device having gradient implant region and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 14/943591
[patent_app_country] => US
[patent_app_date] => 2015-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 43
[patent_no_of_words] => 4614
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14943591
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/943591 | Semiconductor device having gradient implant region and manufacturing method thereof | Nov 16, 2015 | Issued |