Search

Ermias T. Woldegeorgis

Examiner (ID: 9205, Phone: (571)270-5350 , Office: P/2893 )

Most Active Art Unit
2893
Art Unit(s)
2893, 2821
Total Applications
990
Issued Applications
699
Pending Applications
103
Abandoned Applications
225

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9828149 [patent_doc_number] => 08937378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-20 [patent_title] => 'Lead frame and semiconductor package including the same' [patent_app_type] => utility [patent_app_number] => 13/347915 [patent_app_country] => US [patent_app_date] => 2012-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6500 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13347915 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/347915
Lead frame and semiconductor package including the same Jan 10, 2012 Issued
Array ( [id] => 8333277 [patent_doc_number] => 20120199968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/348020 [patent_app_country] => US [patent_app_date] => 2012-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 8960 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13348020 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/348020
SEMICONDUCTOR PACKAGE Jan 10, 2012 Abandoned
Array ( [id] => 10004316 [patent_doc_number] => 09048415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'Memory cells including top electrodes comprising metal silicide, apparatuses including such cells, and related methods' [patent_app_type] => utility [patent_app_number] => 13/347840 [patent_app_country] => US [patent_app_date] => 2012-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 7684 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13347840 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/347840
Memory cells including top electrodes comprising metal silicide, apparatuses including such cells, and related methods Jan 10, 2012 Issued
Array ( [id] => 8914080 [patent_doc_number] => 20130175705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'Stress Compensation Layer for 3D Packaging' [patent_app_type] => utility [patent_app_number] => 13/348449 [patent_app_country] => US [patent_app_date] => 2012-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13348449 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/348449
Stress compensation layer for 3D packaging Jan 10, 2012 Issued
Array ( [id] => 11687354 [patent_doc_number] => 09685404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-20 [patent_title] => 'Back-end electrically programmable fuse' [patent_app_type] => utility [patent_app_number] => 13/348011 [patent_app_country] => US [patent_app_date] => 2012-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 4130 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13348011 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/348011
Back-end electrically programmable fuse Jan 10, 2012 Issued
Array ( [id] => 8818500 [patent_doc_number] => 20130119545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/347570 [patent_app_country] => US [patent_app_date] => 2012-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2915 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13347570 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/347570
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME Jan 9, 2012 Abandoned
Array ( [id] => 8914055 [patent_doc_number] => 20130175680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'DIELECTRIC MATERIAL WITH HIGH MECHANICAL STRENGTH' [patent_app_type] => utility [patent_app_number] => 13/347687 [patent_app_country] => US [patent_app_date] => 2012-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3740 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13347687 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/347687
DIELECTRIC MATERIAL WITH HIGH MECHANICAL STRENGTH Jan 9, 2012 Abandoned
Array ( [id] => 10831895 [patent_doc_number] => 08860067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Semiconductor light emitting device' [patent_app_type] => utility [patent_app_number] => 13/311050 [patent_app_country] => US [patent_app_date] => 2011-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 9334 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13311050 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/311050
Semiconductor light emitting device Dec 4, 2011 Issued
Array ( [id] => 8224899 [patent_doc_number] => 20120139099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'SYSTEM AND METHOD FOR INTEGRATED WAVEGUIDE PACKAGING' [patent_app_type] => utility [patent_app_number] => 13/311235 [patent_app_country] => US [patent_app_date] => 2011-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8104 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13311235 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/311235
System and method for integrated waveguide packaging Dec 4, 2011 Issued
Array ( [id] => 8474392 [patent_doc_number] => 20120273799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME' [patent_app_type] => utility [patent_app_number] => 13/311127 [patent_app_country] => US [patent_app_date] => 2011-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8558 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13311127 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/311127
SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME Dec 4, 2011 Abandoned
Array ( [id] => 8049545 [patent_doc_number] => 20120074505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => '3D Integrated circuit in planar process' [patent_app_type] => utility [patent_app_number] => 13/311115 [patent_app_country] => US [patent_app_date] => 2011-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6139 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20120074505.pdf [firstpage_image] =>[orig_patent_app_number] => 13311115 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/311115
3D Integrated circuit in planar process Dec 4, 2011 Abandoned
Array ( [id] => 8237378 [patent_doc_number] => 20120146117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'SOLID-STATE IMAGING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/311051 [patent_app_country] => US [patent_app_date] => 2011-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4262 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13311051 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/311051
Solid-state imaging device Dec 4, 2011 Issued
Array ( [id] => 8224727 [patent_doc_number] => 20120138928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'Method of Manufacturing Low Resistivity Contacts on n-Type Germanium' [patent_app_type] => utility [patent_app_number] => 13/310945 [patent_app_country] => US [patent_app_date] => 2011-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6017 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13310945 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/310945
Method of manufacturing low resistivity contacts on n-type germanium Dec 4, 2011 Issued
Array ( [id] => 8850838 [patent_doc_number] => 20130140513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'THERMALLY CONFINED ELECTRODE FOR PROGRAMMABLE RESISTANCE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/310583 [patent_app_country] => US [patent_app_date] => 2011-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4676 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13310583 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/310583
Thermally confined electrode for programmable resistance memory Dec 1, 2011 Issued
Array ( [id] => 9711332 [patent_doc_number] => 08835906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Sensor, semiconductor wafer, and method of producing semiconductor wafer' [patent_app_type] => utility [patent_app_number] => 13/310522 [patent_app_country] => US [patent_app_date] => 2011-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 14648 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13310522 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/310522
Sensor, semiconductor wafer, and method of producing semiconductor wafer Dec 1, 2011 Issued
Array ( [id] => 9086851 [patent_doc_number] => 08558281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-15 [patent_title] => 'Gate metallization methods for self-aligned sidewall gate GaN HEMT' [patent_app_type] => utility [patent_app_number] => 13/310473 [patent_app_country] => US [patent_app_date] => 2011-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2668 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13310473 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/310473
Gate metallization methods for self-aligned sidewall gate GaN HEMT Dec 1, 2011 Issued
Array ( [id] => 9711405 [patent_doc_number] => 08835980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Semiconductor wafer, photoelectric conversion device, method of producing semiconductor wafer, and method of producing photoelectric conversion device' [patent_app_type] => utility [patent_app_number] => 13/310614 [patent_app_country] => US [patent_app_date] => 2011-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 14444 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 449 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13310614 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/310614
Semiconductor wafer, photoelectric conversion device, method of producing semiconductor wafer, and method of producing photoelectric conversion device Dec 1, 2011 Issued
Array ( [id] => 8610145 [patent_doc_number] => 20130015457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/310560 [patent_app_country] => US [patent_app_date] => 2011-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6278 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13310560 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/310560
ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME Dec 1, 2011 Abandoned
Array ( [id] => 9504272 [patent_doc_number] => 08742590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Method for forming isolation trenches' [patent_app_type] => utility [patent_app_number] => 13/310521 [patent_app_country] => US [patent_app_date] => 2011-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 7781 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13310521 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/310521
Method for forming isolation trenches Dec 1, 2011 Issued
Array ( [id] => 8850989 [patent_doc_number] => 20130140664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'FLIP CHIP PACKAGING STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/310703 [patent_app_country] => US [patent_app_date] => 2011-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2764 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13310703 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/310703
FLIP CHIP PACKAGING STRUCTURE Dec 1, 2011 Abandoned
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