Search

Ermias T. Woldegeorgis

Examiner (ID: 9205, Phone: (571)270-5350 , Office: P/2893 )

Most Active Art Unit
2893
Art Unit(s)
2893, 2821
Total Applications
990
Issued Applications
699
Pending Applications
103
Abandoned Applications
225

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4749069 [patent_doc_number] => 20080157140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'IMAGE SENSOR AND FABRICATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/869489 [patent_app_country] => US [patent_app_date] => 2007-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157140.pdf [firstpage_image] =>[orig_patent_app_number] => 11869489 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/869489
IMAGE SENSOR AND FABRICATING METHOD THEREOF Oct 8, 2007 Abandoned
Array ( [id] => 5439307 [patent_doc_number] => 20090090946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'DRAM CELL WITH MAGNETIC CAPACITOR' [patent_app_type] => utility [patent_app_number] => 11/868339 [patent_app_country] => US [patent_app_date] => 2007-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2418 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20090090946.pdf [firstpage_image] =>[orig_patent_app_number] => 11868339 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/868339
DRAM CELL WITH MAGNETIC CAPACITOR Oct 4, 2007 Abandoned
Array ( [id] => 185991 [patent_doc_number] => 07646052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'DRAM and SRAM mixedly mounted semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/867198 [patent_app_country] => US [patent_app_date] => 2007-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 4494 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/646/07646052.pdf [firstpage_image] =>[orig_patent_app_number] => 11867198 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/867198
DRAM and SRAM mixedly mounted semiconductor device Oct 3, 2007 Issued
Array ( [id] => 4743721 [patent_doc_number] => 20080088322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Semiconductor device fabrication method and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/905278 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6174 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20080088322.pdf [firstpage_image] =>[orig_patent_app_number] => 11905278 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/905278
Semiconductor device fabrication method and semiconductor device Sep 27, 2007 Abandoned
Array ( [id] => 7713288 [patent_doc_number] => 08093601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Active matrix substrate' [patent_app_type] => utility [patent_app_number] => 12/442870 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8506 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/093/08093601.pdf [firstpage_image] =>[orig_patent_app_number] => 12442870 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/442870
Active matrix substrate Sep 24, 2007 Issued
Array ( [id] => 5271626 [patent_doc_number] => 20090075402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'Manipulation of focused heating source based on in situ optical measurements' [patent_app_type] => utility [patent_app_number] => 11/902027 [patent_app_country] => US [patent_app_date] => 2007-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12901 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20090075402.pdf [firstpage_image] =>[orig_patent_app_number] => 11902027 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/902027
Manipulation of focused heating source based on in situ optical measurements Sep 17, 2007 Abandoned
Array ( [id] => 4866908 [patent_doc_number] => 20080145967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Semiconductor package and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/898717 [patent_app_country] => US [patent_app_date] => 2007-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3734 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20080145967.pdf [firstpage_image] =>[orig_patent_app_number] => 11898717 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/898717
Semiconductor package for fine pitch miniaturization and manufacturing method thereof Sep 13, 2007 Issued
Array ( [id] => 4431912 [patent_doc_number] => 07968430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Compound semiconductor device and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 11/850377 [patent_app_country] => US [patent_app_date] => 2007-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 3629 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/968/07968430.pdf [firstpage_image] =>[orig_patent_app_number] => 11850377 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/850377
Compound semiconductor device and method for manufacturing same Sep 4, 2007 Issued
Array ( [id] => 4651595 [patent_doc_number] => 20080038851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Pattern for evaluating electric characteristics, method for evaluating electric characteristics, method for manufacturing semiconductor device and method for providing reliability assurance' [patent_app_type] => utility [patent_app_number] => 11/889267 [patent_app_country] => US [patent_app_date] => 2007-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5932 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20080038851.pdf [firstpage_image] =>[orig_patent_app_number] => 11889267 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/889267
Pattern for evaluating electric characteristics, method for evaluating electric characteristics, method for manufacturing semiconductor device and method for providing reliability assurance Aug 9, 2007 Abandoned
Array ( [id] => 177802 [patent_doc_number] => 07655510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Manufacturing method of display device and exposure system for that' [patent_app_type] => utility [patent_app_number] => 11/878397 [patent_app_country] => US [patent_app_date] => 2007-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 38 [patent_no_of_words] => 23729 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/655/07655510.pdf [firstpage_image] =>[orig_patent_app_number] => 11878397 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/878397
Manufacturing method of display device and exposure system for that Jul 23, 2007 Issued
Array ( [id] => 4711192 [patent_doc_number] => 20080299718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'DAMASCENE PROCESS HAVING RETAINED CAPPING LAYER THROUGH METALLIZATION FOR PROTECTING LOW-K DIELECTRICS' [patent_app_type] => utility [patent_app_number] => 11/757147 [patent_app_country] => US [patent_app_date] => 2007-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6850 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0299/20080299718.pdf [firstpage_image] =>[orig_patent_app_number] => 11757147 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/757147
DAMASCENE PROCESS HAVING RETAINED CAPPING LAYER THROUGH METALLIZATION FOR PROTECTING LOW-K DIELECTRICS May 31, 2007 Abandoned
Array ( [id] => 4731232 [patent_doc_number] => 20080048260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/756217 [patent_app_country] => US [patent_app_date] => 2007-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 8778 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20080048260.pdf [firstpage_image] =>[orig_patent_app_number] => 11756217 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/756217
Thin film transistor array panel and method of manufacturing the same May 30, 2007 Issued
Array ( [id] => 4711203 [patent_doc_number] => 20080299729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'METHOD OF FABRICATING HIGH VOLTAGE MOS TRANSISTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/754357 [patent_app_country] => US [patent_app_date] => 2007-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2221 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0299/20080299729.pdf [firstpage_image] =>[orig_patent_app_number] => 11754357 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/754357
METHOD OF FABRICATING HIGH VOLTAGE MOS TRANSISTOR DEVICE May 27, 2007 Abandoned
Array ( [id] => 7800990 [patent_doc_number] => 08129260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Semiconductor substrates having low defects and methods of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/802667 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 7107 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/129/08129260.pdf [firstpage_image] =>[orig_patent_app_number] => 11802667 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/802667
Semiconductor substrates having low defects and methods of manufacturing the same May 23, 2007 Issued
Array ( [id] => 4963046 [patent_doc_number] => 20080105866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'Method of fabricating organic thin film transistor using self assembled monolayer-forming compound containing dichlorophosphoryl group' [patent_app_type] => utility [patent_app_number] => 11/802657 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4855 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20080105866.pdf [firstpage_image] =>[orig_patent_app_number] => 11802657 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/802657
Method of fabricating organic thin film transistor using self assembled monolayer-forming compound containing dichlorophosphoryl group May 23, 2007 Abandoned
Array ( [id] => 9576031 [patent_doc_number] => 08766449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Variable interconnect geometry for electronic packages and fabrication methods' [patent_app_type] => utility [patent_app_number] => 11/805693 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 26 [patent_no_of_words] => 3450 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11805693 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/805693
Variable interconnect geometry for electronic packages and fabrication methods May 23, 2007 Issued
Array ( [id] => 5085463 [patent_doc_number] => 20070275514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'Semiconductor device and method of manufacturing same' [patent_app_type] => utility [patent_app_number] => 11/802757 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5847 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20070275514.pdf [firstpage_image] =>[orig_patent_app_number] => 11802757 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/802757
Semiconductor device and method of manufacturing same May 23, 2007 Abandoned
Array ( [id] => 8317408 [patent_doc_number] => 08232183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Process and apparatus for wafer-level flip-chip assembly' [patent_app_type] => utility [patent_app_number] => 11/800387 [patent_app_country] => US [patent_app_date] => 2007-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2268 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11800387 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/800387
Process and apparatus for wafer-level flip-chip assembly May 3, 2007 Issued
Array ( [id] => 4547155 [patent_doc_number] => 07960290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Method of fabricating a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/799637 [patent_app_country] => US [patent_app_date] => 2007-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 31 [patent_no_of_words] => 4718 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/960/07960290.pdf [firstpage_image] =>[orig_patent_app_number] => 11799637 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/799637
Method of fabricating a semiconductor device May 1, 2007 Issued
Array ( [id] => 8859144 [patent_doc_number] => 08461681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'Layered structure for corrosion resistant interconnect contacts' [patent_app_type] => utility [patent_app_number] => 11/741583 [patent_app_country] => US [patent_app_date] => 2007-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6470 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11741583 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/741583
Layered structure for corrosion resistant interconnect contacts Apr 26, 2007 Issued
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