Search

Ermias T. Woldegeorgis

Examiner (ID: 9205, Phone: (571)270-5350 , Office: P/2893 )

Most Active Art Unit
2893
Art Unit(s)
2893, 2821
Total Applications
990
Issued Applications
699
Pending Applications
103
Abandoned Applications
225

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4715338 [patent_doc_number] => 20080237860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'INTERCONNECT STRUCTURES CONTAINING A RUTHENIUM BARRIER FILM AND METHOD OF FORMING' [patent_app_type] => utility [patent_app_number] => 11/691897 [patent_app_country] => US [patent_app_date] => 2007-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5302 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237860.pdf [firstpage_image] =>[orig_patent_app_number] => 11691897 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/691897
INTERCONNECT STRUCTURES CONTAINING A RUTHENIUM BARRIER FILM AND METHOD OF FORMING Mar 26, 2007 Abandoned
Array ( [id] => 4715131 [patent_doc_number] => 20080237653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Deep Implant Self-Aligned To Polysilicon Gate' [patent_app_type] => utility [patent_app_number] => 11/691457 [patent_app_country] => US [patent_app_date] => 2007-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4376 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237653.pdf [firstpage_image] =>[orig_patent_app_number] => 11691457 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/691457
Deep implant self-aligned to polysilicon gate Mar 25, 2007 Issued
Array ( [id] => 8652993 [patent_doc_number] => 08372739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-12 [patent_title] => 'Diffusion barrier for integrated circuits formed from a layer of reactive metal and method of fabrication' [patent_app_type] => utility [patent_app_number] => 11/691167 [patent_app_country] => US [patent_app_date] => 2007-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4120 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11691167 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/691167
Diffusion barrier for integrated circuits formed from a layer of reactive metal and method of fabrication Mar 25, 2007 Issued
Array ( [id] => 4740050 [patent_doc_number] => 20080233703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'POLYSILICON CONDUCTIVITY IMPROVEMENT IN A SALICIDE PROCESS TECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 11/689267 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2826 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20080233703.pdf [firstpage_image] =>[orig_patent_app_number] => 11689267 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/689267
POLYSILICON CONDUCTIVITY IMPROVEMENT IN A SALICIDE PROCESS TECHNOLOGY Mar 20, 2007 Abandoned
Array ( [id] => 4570837 [patent_doc_number] => 07847395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Package and package assembly of power device' [patent_app_type] => utility [patent_app_number] => 11/680061 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2842 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/847/07847395.pdf [firstpage_image] =>[orig_patent_app_number] => 11680061 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/680061
Package and package assembly of power device Feb 27, 2007 Issued
Array ( [id] => 132745 [patent_doc_number] => 07701012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Complementary zener triggered bipolar ESD protection' [patent_app_type] => utility [patent_app_number] => 11/678962 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 5914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/701/07701012.pdf [firstpage_image] =>[orig_patent_app_number] => 11678962 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/678962
Complementary zener triggered bipolar ESD protection Feb 25, 2007 Issued
Array ( [id] => 233164 [patent_doc_number] => 07598592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Capacitor structure for integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/675721 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3343 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/598/07598592.pdf [firstpage_image] =>[orig_patent_app_number] => 11675721 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675721
Capacitor structure for integrated circuit Feb 15, 2007 Issued
Array ( [id] => 4768717 [patent_doc_number] => 20080054373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'POWER SEMICONDUCTION DEVICE AND CIRCUIT MODULE HAVING SUCH POWER SEMICONDUCTION DEVICE' [patent_app_type] => utility [patent_app_number] => 11/675511 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20080054373.pdf [firstpage_image] =>[orig_patent_app_number] => 11675511 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675511
POWER SEMICONDUCTION DEVICE AND CIRCUIT MODULE HAVING SUCH POWER SEMICONDUCTION DEVICE Feb 14, 2007 Abandoned
Array ( [id] => 5233861 [patent_doc_number] => 20070126016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'LIGHT EMITTING DEVICE AND MANUFACTURE METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/674371 [patent_app_country] => US [patent_app_date] => 2007-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3750 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20070126016.pdf [firstpage_image] =>[orig_patent_app_number] => 11674371 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/674371
LIGHT EMITTING DEVICE AND MANUFACTURE METHOD THEREOF Feb 12, 2007 Abandoned
Array ( [id] => 5255246 [patent_doc_number] => 20070136702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'SEMICONDUCTOR DEVICE LAYOUT INSPECTION METHOD' [patent_app_type] => utility [patent_app_number] => 11/673480 [patent_app_country] => US [patent_app_date] => 2007-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 16272 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20070136702.pdf [firstpage_image] =>[orig_patent_app_number] => 11673480 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/673480
SEMICONDUCTOR DEVICE LAYOUT INSPECTION METHOD Feb 8, 2007 Abandoned
Array ( [id] => 4846020 [patent_doc_number] => 20080182428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'ELECTRONIC DEVICE INCLUDING A LAYER OF DISCONTINUOUS STORAGE ELEMENTS AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 11/627817 [patent_app_country] => US [patent_app_date] => 2007-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20080182428.pdf [firstpage_image] =>[orig_patent_app_number] => 11627817 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/627817
Process of forming an electronic device including a layer of discontinuous storage elements Jan 25, 2007 Issued
Array ( [id] => 4651625 [patent_doc_number] => 20080038881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Thin Film Transistor Array Panel and Manufacturing Method Thereof' [patent_app_type] => utility [patent_app_number] => 11/621807 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4210 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20080038881.pdf [firstpage_image] =>[orig_patent_app_number] => 11621807 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/621807
Thin Film Transistor Array Panel and Manufacturing Method Thereof Jan 9, 2007 Abandoned
Array ( [id] => 5101323 [patent_doc_number] => 20070184585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/620527 [patent_app_country] => US [patent_app_date] => 2007-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7402 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20070184585.pdf [firstpage_image] =>[orig_patent_app_number] => 11620527 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/620527
Method for manufacturing semiconductor device Jan 4, 2007 Issued
Array ( [id] => 4932953 [patent_doc_number] => 20080003728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/619407 [patent_app_country] => US [patent_app_date] => 2007-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6106 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20080003728.pdf [firstpage_image] =>[orig_patent_app_number] => 11619407 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/619407
THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME Jan 2, 2007 Abandoned
Array ( [id] => 4749330 [patent_doc_number] => 20080157401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE WITH TOP PAD' [patent_app_type] => utility [patent_app_number] => 11/618805 [patent_app_country] => US [patent_app_date] => 2006-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157401.pdf [firstpage_image] =>[orig_patent_app_number] => 11618805 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618805
Integrated circuit package with top pad Dec 29, 2006 Issued
Array ( [id] => 8178334 [patent_doc_number] => 08178982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-15 [patent_title] => 'Dual molded multi-chip package system' [patent_app_type] => utility [patent_app_number] => 11/618806 [patent_app_country] => US [patent_app_date] => 2006-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 25 [patent_no_of_words] => 5095 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/178/08178982.pdf [firstpage_image] =>[orig_patent_app_number] => 11618806 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618806
Dual molded multi-chip package system Dec 29, 2006 Issued
Array ( [id] => 4749249 [patent_doc_number] => 20080157320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Laterally Interconnected IC Packages and Methods' [patent_app_type] => utility [patent_app_number] => 11/617906 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1938 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157320.pdf [firstpage_image] =>[orig_patent_app_number] => 11617906 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/617906
Laterally Interconnected IC Packages and Methods Dec 28, 2006 Abandoned
Array ( [id] => 4749226 [patent_doc_number] => 20080157297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Stress-Resistant Leadframe and Method' [patent_app_type] => utility [patent_app_number] => 11/618275 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2347 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157297.pdf [firstpage_image] =>[orig_patent_app_number] => 11618275 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618275
Stress-Resistant Leadframe and Method Dec 28, 2006 Abandoned
Array ( [id] => 4654949 [patent_doc_number] => 20080023809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'CHIP PACKAGE AND DIGITAL CAMERA MODULE USING SAME' [patent_app_type] => utility [patent_app_number] => 11/616837 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2543 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20080023809.pdf [firstpage_image] =>[orig_patent_app_number] => 11616837 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616837
CHIP PACKAGE AND DIGITAL CAMERA MODULE USING SAME Dec 26, 2006 Abandoned
Array ( [id] => 4768791 [patent_doc_number] => 20080054447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'CHIP PACKAGE AND DIGITAL CAMERA MODULE USING SAME' [patent_app_type] => utility [patent_app_number] => 11/616838 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2694 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20080054447.pdf [firstpage_image] =>[orig_patent_app_number] => 11616838 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616838
CHIP PACKAGE AND DIGITAL CAMERA MODULE USING SAME Dec 26, 2006 Abandoned
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