Search

Ernest F Karlsen

Examiner (ID: 15544)

Most Active Art Unit
2607
Art Unit(s)
2607, 2858, 2504, 2508, 2213, 2829, 2899, 2604
Total Applications
2295
Issued Applications
1990
Pending Applications
49
Abandoned Applications
256

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16448394 [patent_doc_number] => 10840325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Low resistance metal-insulator-metal capacitor electrode [patent_app_type] => utility [patent_app_number] => 15/950209 [patent_app_country] => US [patent_app_date] => 2018-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 19 [patent_no_of_words] => 4673 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950209 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/950209
Low resistance metal-insulator-metal capacitor electrode Apr 10, 2018 Issued
Array ( [id] => 14984949 [patent_doc_number] => 10446395 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-15 [patent_title] => Self-aligned multiple patterning processes with layered mandrels [patent_app_type] => utility [patent_app_number] => 15/950364 [patent_app_country] => US [patent_app_date] => 2018-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4056 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950364 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/950364
Self-aligned multiple patterning processes with layered mandrels Apr 10, 2018 Issued
Array ( [id] => 15000097 [patent_doc_number] => 20190319006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => NANOWIRE ENABLED SUBSTRATE BONDING AND ELECTRICAL CONTACT FORMATION [patent_app_type] => utility [patent_app_number] => 15/950239 [patent_app_country] => US [patent_app_date] => 2018-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5797 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950239 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/950239
Nanowire enabled substrate bonding and electrical contact formation Apr 10, 2018 Issued
Array ( [id] => 15000165 [patent_doc_number] => 20190319040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE CONTAINING BIDIRECTIONAL TAPER STAIRCASES AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 15/950356 [patent_app_country] => US [patent_app_date] => 2018-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950356 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/950356
Three-dimensional memory device containing bidirectional taper staircases and methods of making the same Apr 10, 2018 Issued
Array ( [id] => 14707029 [patent_doc_number] => 10381273 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-13 [patent_title] => Vertically stacked multi-channel transistor structure [patent_app_type] => utility [patent_app_number] => 15/950372 [patent_app_country] => US [patent_app_date] => 2018-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9516 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950372 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/950372
Vertically stacked multi-channel transistor structure Apr 10, 2018 Issued
Array ( [id] => 13499781 [patent_doc_number] => 20180301433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => EMISSIVE LED DISPLAY DEVICE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 15/949184 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949184 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949184
EMISSIVE LED DISPLAY DEVICE MANUFACTURING METHOD Apr 9, 2018 Abandoned
Array ( [id] => 14221219 [patent_doc_number] => 20190122994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 15/950000 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950000 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/950000
SEMICONDUCTOR PACKAGE Apr 9, 2018 Abandoned
Array ( [id] => 14968967 [patent_doc_number] => 20190311962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => HETEROGENEOUS INTEGRATED CIRCUITS WITH INTEGRATED COVERS [patent_app_type] => utility [patent_app_number] => 15/949159 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949159 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949159
HETEROGENEOUS INTEGRATED CIRCUITS WITH INTEGRATED COVERS Apr 9, 2018 Abandoned
Array ( [id] => 13559153 [patent_doc_number] => 20180331124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/949938 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949938 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949938
Display device Apr 9, 2018 Issued
Array ( [id] => 14969081 [patent_doc_number] => 20190312019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => TECHNIQUES FOR DIE TILING [patent_app_type] => utility [patent_app_number] => 15/949141 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5888 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949141 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949141
TECHNIQUES FOR DIE TILING Apr 9, 2018 Pending
Array ( [id] => 14969143 [patent_doc_number] => 20190312050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => STRING SELECT LINE GATE OXIDE METHOD FOR 3D VERTICAL CHANNEL NAND MEMORY [patent_app_type] => utility [patent_app_number] => 15/950021 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950021 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/950021
STRING SELECT LINE GATE OXIDE METHOD FOR 3D VERTICAL CHANNEL NAND MEMORY Apr 9, 2018 Abandoned
Array ( [id] => 14969415 [patent_doc_number] => 20190312186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => Side-Emitting LED with Increased Illumination [patent_app_type] => utility [patent_app_number] => 15/948660 [patent_app_country] => US [patent_app_date] => 2018-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15948660 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/948660
Side-Emitting LED with Increased Illumination Apr 8, 2018 Abandoned
Array ( [id] => 13938615 [patent_doc_number] => 20190052823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => IMAGE SENSOR FOR COMPENSATING FOR SIGNAL DIFFERENCE BETWEEN PIXELS [patent_app_type] => utility [patent_app_number] => 15/948756 [patent_app_country] => US [patent_app_date] => 2018-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15948756 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/948756
Image sensor for compensating for signal difference between pixels Apr 8, 2018 Issued
Array ( [id] => 14671941 [patent_doc_number] => 10373890 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-06 [patent_title] => Cooling techniques for semiconductor package [patent_app_type] => utility [patent_app_number] => 15/948747 [patent_app_country] => US [patent_app_date] => 2018-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 36 [patent_no_of_words] => 10628 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15948747 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/948747
Cooling techniques for semiconductor package Apr 8, 2018 Issued
Array ( [id] => 14509731 [patent_doc_number] => 20190198520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => Memory Arrays [patent_app_type] => utility [patent_app_number] => 15/948639 [patent_app_country] => US [patent_app_date] => 2018-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15948639 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/948639
Memory arrays Apr 8, 2018 Issued
Array ( [id] => 13514431 [patent_doc_number] => 20180308758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => Methods of Forming Sources and Drains for FinFETs Using Solid Phase Epitaxy With Laser Annealing [patent_app_type] => utility [patent_app_number] => 15/948627 [patent_app_country] => US [patent_app_date] => 2018-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15948627 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/948627
Methods of Forming Sources and Drains for FinFETs Using Solid Phase Epitaxy With Laser Annealing Apr 8, 2018 Abandoned
Array ( [id] => 15641783 [patent_doc_number] => 10593905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Organic light emitting display device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/943967 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 11473 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943967 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943967
Organic light emitting display device and method of manufacturing the same Apr 2, 2018 Issued
Array ( [id] => 16578843 [patent_doc_number] => 20210013244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => ACTIVE-MATRIX SUBSTRATE AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/980172 [patent_app_country] => US [patent_app_date] => 2018-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16980172 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/980172
Active-matrix substrate and display device Mar 14, 2018 Issued
Array ( [id] => 13629853 [patent_doc_number] => 20180366479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => Hybrid Electronically Erasable Programmable Read-Only Memory (EEPROM) Systems And Methods For Forming Related Applications [patent_app_type] => utility [patent_app_number] => 15/913286 [patent_app_country] => US [patent_app_date] => 2018-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15913286 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/913286
Hybrid electronically erasable programmable read-only memory (EEPROM) systems and methods for forming related applications Mar 5, 2018 Issued
Array ( [id] => 15475381 [patent_doc_number] => 10553576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Method for filling patterns [patent_app_type] => utility [patent_app_number] => 15/891312 [patent_app_country] => US [patent_app_date] => 2018-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2791 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15891312 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/891312
Method for filling patterns Feb 6, 2018 Issued
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