Search

Ernest Unelus

Examiner (ID: 8567, Phone: (571)272-8596 , Office: P/2181 )

Most Active Art Unit
2181
Art Unit(s)
2828, 2181
Total Applications
750
Issued Applications
562
Pending Applications
44
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20557119 [patent_doc_number] => 20260056905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-26 [patent_title] => UALink Non-Transparent Memory Bridging for AI Infrastructures Comprising GPUs, Accelerators, and Memory Switches [patent_app_type] => utility [patent_app_number] => 19/371779 [patent_app_country] => US [patent_app_date] => 2025-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 193940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19371779 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/371779
UALink non-transparent memory bridging for AI infrastructures comprising GPUs, accelerators, and memory switches Oct 27, 2025 Issued
Array ( [id] => 20428359 [patent_doc_number] => 20250390451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => SYSTEMS AND METHODS FOR MITIGATING LATENCY IN INPUT/OUTPUT TRANSACTIONS [patent_app_type] => utility [patent_app_number] => 19/215719 [patent_app_country] => US [patent_app_date] => 2025-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19215719 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/215719
SYSTEMS AND METHODS FOR MITIGATING LATENCY IN INPUT/OUTPUT TRANSACTIONS May 21, 2025 Pending
Array ( [id] => 19756383 [patent_doc_number] => 20250044948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => DYNAMIC TEMPERATURE COMPENSATION IN A MEMORY COMPONENT [patent_app_type] => utility [patent_app_number] => 18/920580 [patent_app_country] => US [patent_app_date] => 2024-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18920580 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/920580
DYNAMIC TEMPERATURE COMPENSATION IN A MEMORY COMPONENT Oct 17, 2024 Pending
Array ( [id] => 19644826 [patent_doc_number] => 20240419346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => INPUT/OUTPUT OPERATIONS PER SECOND (IOPS) AND THROUGHPUT MONITORING FOR DYNAMIC AND OPTIMAL RESOURCE ALLOCATION [patent_app_type] => utility [patent_app_number] => 18/821335 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16135 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18821335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/821335
INPUT/OUTPUT OPERATIONS PER SECOND (IOPS) AND THROUGHPUT MONITORING FOR DYNAMIC AND OPTIMAL RESOURCE ALLOCATION Aug 29, 2024 Pending
Array ( [id] => 19933578 [patent_doc_number] => 12306782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Peer arrangements among switch-coupled endpoint devices [patent_app_type] => utility [patent_app_number] => 18/741282 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 10799 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741282 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741282
Peer arrangements among switch-coupled endpoint devices Jun 11, 2024 Issued
Array ( [id] => 20408689 [patent_doc_number] => 20250377798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-11 [patent_title] => MEMORY MODULES WITH RANDOM ACCESS MEMORY (RAM) MEMORY CHIPS SUPPORTING DISTINCT, MULTIPLE SINGLE-WORD MEMORY ACCESSES, AND RELATED MEMORY SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 18/737046 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18737046 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/737046
MEMORY MODULES WITH RANDOM ACCESS MEMORY (RAM) MEMORY CHIPS SUPPORTING DISTINCT, MULTIPLE SINGLE-WORD MEMORY ACCESSES, AND RELATED MEMORY SYSTEMS AND METHODS Jun 6, 2024 Pending
Array ( [id] => 19756633 [patent_doc_number] => 20250045198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => ACCELERATING COMMAND LATENCIES USING A HYBRID COMPUTE EXPRESS LINK TYPE-3 SSD MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/678973 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18678973 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/678973
ACCELERATING COMMAND LATENCIES USING A HYBRID COMPUTE EXPRESS LINK TYPE-3 SSD MEMORY DEVICE May 29, 2024 Pending
Array ( [id] => 19450893 [patent_doc_number] => 20240311023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => DATA STORAGE DEVICE WITH NOISE INJECTION [patent_app_type] => utility [patent_app_number] => 18/670512 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670512 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670512
DATA STORAGE DEVICE WITH NOISE INJECTION May 20, 2024 Pending
Array ( [id] => 20365859 [patent_doc_number] => 20250355671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => MANAGING MOTHERBOARD REPLACEMENT AT AN INFORMATION HANDLING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/664429 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664429 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664429
MANAGING MOTHERBOARD REPLACEMENT AT AN INFORMATION HANDLING SYSTEM May 14, 2024 Pending
Array ( [id] => 20310716 [patent_doc_number] => 20250328345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => SYSTEM-INTEGRATED SOLUTION FOR IO DEVICE EXTENDED CONTROL WITHOUT OPERATING SYSTEM DRIVER INVOLVEMENT [patent_app_type] => utility [patent_app_number] => 18/642379 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642379 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/642379
SYSTEM-INTEGRATED SOLUTION FOR IO DEVICE EXTENDED CONTROL WITHOUT OPERATING SYSTEM DRIVER INVOLVEMENT Apr 21, 2024 Pending
Array ( [id] => 20290151 [patent_doc_number] => 20250315394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => SECURE, SCALABLE DOORBELL MECHANISM BETWEEN PEERS IN A PCIE FABRIC [patent_app_type] => utility [patent_app_number] => 18/630387 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630387 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/630387
SECURE, SCALABLE DOORBELL MECHANISM BETWEEN PEERS IN A PCIE FABRIC Apr 8, 2024 Pending
Array ( [id] => 19320097 [patent_doc_number] => 20240241641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => PACKET ROUTING BETWEEN MEMORY DEVICES AND RELATED APPARATUSES, METHODS, AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/618966 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618966 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/618966
Packet routing between memory devices and related apparatuses, methods, and memory systems Mar 26, 2024 Issued
Array ( [id] => 19391271 [patent_doc_number] => 20240281141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => MEMORY CONTROLLER WITH TIME-BASED READ AND WRITE PHASES [patent_app_type] => utility [patent_app_number] => 18/443956 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10937 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443956 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443956
MEMORY CONTROLLER WITH TIME-BASED READ AND WRITE PHASES Feb 15, 2024 Pending
Array ( [id] => 19383178 [patent_doc_number] => 20240273048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => DATA OPERATION SYSTEM, DATA OPERATION METHOD, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/442637 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7037 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442637 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442637
DATA OPERATION SYSTEM, DATA OPERATION METHOD, AND STORAGE MEDIUM Feb 14, 2024 Pending
Array ( [id] => 19451138 [patent_doc_number] => 20240311268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => CONTROL PROGRAM, CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 18/439857 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439857 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/439857
CONTROL PROGRAM, CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS Feb 12, 2024 Pending
Array ( [id] => 19419866 [patent_doc_number] => 20240295989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => NONVOLATILE MEMORY PACKAGE, STORAGE DEVICE INCLUDING THE SAME, AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/538512 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538512 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/538512
NONVOLATILE MEMORY PACKAGE, STORAGE DEVICE INCLUDING THE SAME, AND METHOD OF OPERATING THE SAME Dec 12, 2023 Pending
Array ( [id] => 19819256 [patent_doc_number] => 20250077463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => RESERVATION OF PCIe SLOTS FOR MANAGEMENT BY A RAID DRIVER [patent_app_type] => utility [patent_app_number] => 18/527579 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527579 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527579
Reservation of PCIe slots for management by a raid driver Dec 3, 2023 Issued
Array ( [id] => 19466391 [patent_doc_number] => 20240320061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => METHOD AND SYSTEM FOR CONTROLLING ACCESS TO SHARED RESOURCES [patent_app_type] => utility [patent_app_number] => 18/528160 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528160 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528160
METHOD AND SYSTEM FOR CONTROLLING ACCESS TO SHARED RESOURCES Dec 3, 2023 Pending
Array ( [id] => 19267449 [patent_doc_number] => 20240211152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => DISTRIBUTED MEMORY DATA PATH FOR CIRCUIT UNDER ARRAY [patent_app_type] => utility [patent_app_number] => 18/524739 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524739 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524739
Distributed memory data path for circuit under array Nov 29, 2023 Issued
Array ( [id] => 20922681 [patent_doc_number] => 12717742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-25 [patent_title] => Communication system with improved signal delay and slave device and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/494971 [patent_app_country] => US [patent_app_date] => 2023-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18494971 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/494971
COMMUNICATION SYSTEM WITH IMPROVED SIGNAL DELAY AND SLAVE DEVICE AND OPERATING METHOD THEREOF Oct 25, 2023 Pending
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