
Eron J. Sorrell
Examiner (ID: 18678, Phone: (571)272-4160 , Office: P/3992 )
| Most Active Art Unit | 2182 |
| Art Unit(s) | 3992, 2465, 2181, 2182 |
| Total Applications | 655 |
| Issued Applications | 467 |
| Pending Applications | 78 |
| Abandoned Applications | 114 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5621310
[patent_doc_number] => 20060190845
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-24
[patent_title] => 'Portable storage devices'
[patent_app_type] => utility
[patent_app_number] => 11/053861
[patent_app_country] => US
[patent_app_date] => 2005-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2124
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0190/20060190845.pdf
[firstpage_image] =>[orig_patent_app_number] => 11053861
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/053861 | Portable storage devices | Feb 9, 2005 | Abandoned |
Array
(
[id] => 597964
[patent_doc_number] => 07451248
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-11-11
[patent_title] => 'Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations'
[patent_app_type] => utility
[patent_app_number] => 11/054183
[patent_app_country] => US
[patent_app_date] => 2005-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2032
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/451/07451248.pdf
[firstpage_image] =>[orig_patent_app_number] => 11054183
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/054183 | Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations | Feb 8, 2005 | Issued |
Array
(
[id] => 5773841
[patent_doc_number] => 20050267963
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-01
[patent_title] => 'Method for managing I/O interface modules in a computer system'
[patent_app_type] => utility
[patent_app_number] => 11/053260
[patent_app_country] => US
[patent_app_date] => 2005-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 4348
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0267/20050267963.pdf
[firstpage_image] =>[orig_patent_app_number] => 11053260
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/053260 | Method of managing I/O interface modules in a computer system | Feb 8, 2005 | Issued |
Array
(
[id] => 7193362
[patent_doc_number] => 20050193228
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-01
[patent_title] => 'Redundant path control apparatus and redundant path control method'
[patent_app_type] => utility
[patent_app_number] => 11/049886
[patent_app_country] => US
[patent_app_date] => 2005-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6263
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0193/20050193228.pdf
[firstpage_image] =>[orig_patent_app_number] => 11049886
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/049886 | Redundant path control apparatus and redundant path control method | Feb 3, 2005 | Issued |
Array
(
[id] => 7052416
[patent_doc_number] => 20050188135
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-25
[patent_title] => 'High performance serial bus data recorder'
[patent_app_type] => utility
[patent_app_number] => 11/046888
[patent_app_country] => US
[patent_app_date] => 2005-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2535
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0188/20050188135.pdf
[firstpage_image] =>[orig_patent_app_number] => 11046888
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/046888 | High performance serial bus data recorder | Jan 31, 2005 | Abandoned |
Array
(
[id] => 7006734
[patent_doc_number] => 20050172047
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-04
[patent_title] => 'Fibre channel controller shareable by a plurality of operating system domains within a load-store architecture'
[patent_app_type] => utility
[patent_app_number] => 11/046564
[patent_app_country] => US
[patent_app_date] => 2005-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 23665
[patent_no_of_claims] => 67
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0172/20050172047.pdf
[firstpage_image] =>[orig_patent_app_number] => 11046564
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/046564 | Fibre channel controller shareable by a plurality of operating system domains within a load-store architecture | Jan 26, 2005 | Issued |
Array
(
[id] => 7693027
[patent_doc_number] => 20070016659
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-18
[patent_title] => 'Network-based system for configuring a programmable hardware element in a system using hardware configuration programs generated based on a user specification'
[patent_app_type] => utility
[patent_app_number] => 11/037652
[patent_app_country] => US
[patent_app_date] => 2005-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 28750
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0016/20070016659.pdf
[firstpage_image] =>[orig_patent_app_number] => 11037652
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/037652 | Network-based system for configuring a programmable hardware element in a system using hardware configuration programs generated based on a user specification | Jan 17, 2005 | Issued |
Array
(
[id] => 7049551
[patent_doc_number] => 20050185438
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-25
[patent_title] => 'Low profile removable memory module'
[patent_app_type] => utility
[patent_app_number] => 11/031369
[patent_app_country] => US
[patent_app_date] => 2005-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5078
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0185/20050185438.pdf
[firstpage_image] =>[orig_patent_app_number] => 11031369
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/031369 | Low profile removable memory module | Jan 5, 2005 | Abandoned |
Array
(
[id] => 283806
[patent_doc_number] => 07555568
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-30
[patent_title] => 'Method and apparatus for operating a host computer from a portable apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/008326
[patent_app_country] => US
[patent_app_date] => 2004-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 9471
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/555/07555568.pdf
[firstpage_image] =>[orig_patent_app_number] => 11008326
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/008326 | Method and apparatus for operating a host computer from a portable apparatus | Dec 8, 2004 | Issued |
Array
(
[id] => 7157260
[patent_doc_number] => 20050083853
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'System, method, and program for determining the availability of paths to a device'
[patent_app_type] => utility
[patent_app_number] => 11/005967
[patent_app_country] => US
[patent_app_date] => 2004-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8315
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0083/20050083853.pdf
[firstpage_image] =>[orig_patent_app_number] => 11005967
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/005967 | Method for determining the availability of paths to a device | Dec 5, 2004 | Issued |
Array
(
[id] => 6992397
[patent_doc_number] => 20050091434
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format'
[patent_app_type] => utility
[patent_app_number] => 10/996016
[patent_app_country] => US
[patent_app_date] => 2004-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5233
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20050091434.pdf
[firstpage_image] =>[orig_patent_app_number] => 10996016
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/996016 | Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format | Nov 22, 2004 | Issued |
Array
(
[id] => 4580945
[patent_doc_number] => 07840729
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-23
[patent_title] => 'Recording medium access device and recording medium access method'
[patent_app_type] => utility
[patent_app_number] => 10/579803
[patent_app_country] => US
[patent_app_date] => 2004-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 8853
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/840/07840729.pdf
[firstpage_image] =>[orig_patent_app_number] => 10579803
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/579803 | Recording medium access device and recording medium access method | Nov 17, 2004 | Issued |
Array
(
[id] => 7100227
[patent_doc_number] => 20050132104
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-16
[patent_title] => 'Command processing systems and methods'
[patent_app_type] => utility
[patent_app_number] => 10/991905
[patent_app_country] => US
[patent_app_date] => 2004-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10494
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0132/20050132104.pdf
[firstpage_image] =>[orig_patent_app_number] => 10991905
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/991905 | Command processing systems and methods | Nov 16, 2004 | Abandoned |
Array
(
[id] => 5638866
[patent_doc_number] => 20060069840
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-30
[patent_title] => 'Universal serial bus device'
[patent_app_type] => utility
[patent_app_number] => 10/975666
[patent_app_country] => US
[patent_app_date] => 2004-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7051
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0069/20060069840.pdf
[firstpage_image] =>[orig_patent_app_number] => 10975666
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/975666 | Universal serial bus device including a USB connector and a transmitter | Oct 27, 2004 | Issued |
Array
(
[id] => 220291
[patent_doc_number] => 07613853
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-03
[patent_title] => 'Output buffer circuit capable of synchronous and asynchronous data buffering using sensing circuit, and method and system of same'
[patent_app_type] => utility
[patent_app_number] => 10/973812
[patent_app_country] => US
[patent_app_date] => 2004-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2435
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/613/07613853.pdf
[firstpage_image] =>[orig_patent_app_number] => 10973812
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/973812 | Output buffer circuit capable of synchronous and asynchronous data buffering using sensing circuit, and method and system of same | Oct 24, 2004 | Issued |
Array
(
[id] => 823290
[patent_doc_number] => 07409475
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-05
[patent_title] => 'System and method for a high-speed shift-type buffer'
[patent_app_type] => utility
[patent_app_number] => 10/969415
[patent_app_country] => US
[patent_app_date] => 2004-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7904
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/409/07409475.pdf
[firstpage_image] =>[orig_patent_app_number] => 10969415
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/969415 | System and method for a high-speed shift-type buffer | Oct 19, 2004 | Issued |
Array
(
[id] => 5816474
[patent_doc_number] => 20060085565
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-20
[patent_title] => 'Method of configuring device property of storage device for a windows operating system'
[patent_app_type] => utility
[patent_app_number] => 10/966516
[patent_app_country] => US
[patent_app_date] => 2004-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 1947
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0085/20060085565.pdf
[firstpage_image] =>[orig_patent_app_number] => 10966516
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/966516 | Method of configuring device property of storage device for a windows operating system | Oct 17, 2004 | Abandoned |
Array
(
[id] => 7084700
[patent_doc_number] => 20050050080
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-03
[patent_title] => 'Flexible apparatus for setting configurations using an EEPROM'
[patent_app_type] => utility
[patent_app_number] => 10/965211
[patent_app_country] => US
[patent_app_date] => 2004-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1990
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0050/20050050080.pdf
[firstpage_image] =>[orig_patent_app_number] => 10965211
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/965211 | Flexible apparatus for setting configurations using an EEPROM | Oct 14, 2004 | Issued |
Array
(
[id] => 7107141
[patent_doc_number] => 20050108441
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-19
[patent_title] => 'Multimedia audio and video player device'
[patent_app_type] => utility
[patent_app_number] => 10/962503
[patent_app_country] => US
[patent_app_date] => 2004-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2175
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20050108441.pdf
[firstpage_image] =>[orig_patent_app_number] => 10962503
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/962503 | Multimedia audio and video player device | Oct 12, 2004 | Abandoned |
Array
(
[id] => 156164
[patent_doc_number] => 07680966
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-03-16
[patent_title] => 'Memory interface including generation of timing signals for memory operation'
[patent_app_type] => utility
[patent_app_number] => 10/933697
[patent_app_country] => US
[patent_app_date] => 2004-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 23
[patent_no_of_words] => 20134
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/680/07680966.pdf
[firstpage_image] =>[orig_patent_app_number] => 10933697
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/933697 | Memory interface including generation of timing signals for memory operation | Sep 2, 2004 | Issued |