
Errol V. Fernandes
Examiner (ID: 15300, Phone: (571)270-7433 , Office: P/2894 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2894, 2821, 2893 |
| Total Applications | 1197 |
| Issued Applications | 1012 |
| Pending Applications | 72 |
| Abandoned Applications | 130 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18068347
[patent_doc_number] => 20220399435
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-15
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/592862
[patent_app_country] => US
[patent_app_date] => 2022-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8851
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17592862
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/592862 | Semiconductor device and method for fabricating the same | Feb 3, 2022 | Issued |
Array
(
[id] => 19054839
[patent_doc_number] => 20240096808
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => SEMICONDUCTOR PACKAGE, MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE, AND INTERPOSER GROUP
[patent_app_type] => utility
[patent_app_number] => 18/264281
[patent_app_country] => US
[patent_app_date] => 2022-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16509
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18264281
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/264281 | SEMICONDUCTOR PACKAGE, MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE, AND INTERPOSER GROUP | Jan 30, 2022 | Pending |
Array
(
[id] => 18205533
[patent_doc_number] => 11587939
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-21
[patent_title] => Etch method for opening a source line in flash memory
[patent_app_type] => utility
[patent_app_number] => 17/586542
[patent_app_country] => US
[patent_app_date] => 2022-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 41
[patent_no_of_words] => 13833
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17586542
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/586542 | Etch method for opening a source line in flash memory | Jan 26, 2022 | Issued |
Array
(
[id] => 18371824
[patent_doc_number] => 11652006
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-16
[patent_title] => FinFET complementary metal-oxide-semiconductor (CMOS) devices
[patent_app_type] => utility
[patent_app_number] => 17/577835
[patent_app_country] => US
[patent_app_date] => 2022-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 7681
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577835
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/577835 | FinFET complementary metal-oxide-semiconductor (CMOS) devices | Jan 17, 2022 | Issued |
Array
(
[id] => 19796271
[patent_doc_number] => 12237240
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-25
[patent_title] => Semiconductor package and method of manufacturing semiconductor package
[patent_app_type] => utility
[patent_app_number] => 17/573426
[patent_app_country] => US
[patent_app_date] => 2022-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 32
[patent_no_of_words] => 11398
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573426
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/573426 | Semiconductor package and method of manufacturing semiconductor package | Jan 10, 2022 | Issued |
Array
(
[id] => 17566525
[patent_doc_number] => 20220130674
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-28
[patent_title] => DEVICE AND METHOD FOR BONDING OF SUBSTRATES
[patent_app_type] => utility
[patent_app_number] => 17/567942
[patent_app_country] => US
[patent_app_date] => 2022-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12175
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567942
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/567942 | Device and method for bonding of substrates | Jan 3, 2022 | Issued |
Array
(
[id] => 19812425
[patent_doc_number] => 12243838
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-04
[patent_title] => Circuit substrate structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/567883
[patent_app_country] => US
[patent_app_date] => 2022-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 4928
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567883
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/567883 | Circuit substrate structure and manufacturing method thereof | Jan 3, 2022 | Issued |
Array
(
[id] => 17723459
[patent_doc_number] => 20220216181
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-07
[patent_title] => SYSTEM-IN-PACKAGE CHIP OF PRINTER DRIVER SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/559025
[patent_app_country] => US
[patent_app_date] => 2021-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4183
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559025
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/559025 | System-in-package chip of printer driver system | Dec 21, 2021 | Issued |
Array
(
[id] => 19428223
[patent_doc_number] => 12087657
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-10
[patent_title] => Semiconductor packages
[patent_app_type] => utility
[patent_app_number] => 17/551710
[patent_app_country] => US
[patent_app_date] => 2021-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8568
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551710
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/551710 | Semiconductor packages | Dec 14, 2021 | Issued |
Array
(
[id] => 18440032
[patent_doc_number] => 20230187327
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-15
[patent_title] => LEADLESS SEMICONDUCTOR PACKAGE WITH INTERNAL GULL WING LEAD STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 17/551370
[patent_app_country] => US
[patent_app_date] => 2021-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5554
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551370
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/551370 | Leadless semiconductor package with internal gull wing lead structures | Dec 14, 2021 | Issued |
Array
(
[id] => 17963699
[patent_doc_number] => 20220344280
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-27
[patent_title] => INTERPOSER WITH WARPAGE-RELIEF TRENCHES
[patent_app_type] => utility
[patent_app_number] => 17/547218
[patent_app_country] => US
[patent_app_date] => 2021-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11631
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547218
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/547218 | Interposer with warpage-relief trenches | Dec 8, 2021 | Issued |
Array
(
[id] => 19943639
[patent_doc_number] => 12315775
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-27
[patent_title] => Underfill vacuum process
[patent_app_type] => utility
[patent_app_number] => 17/543072
[patent_app_country] => US
[patent_app_date] => 2021-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 20
[patent_no_of_words] => 3473
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543072
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/543072 | Underfill vacuum process | Dec 5, 2021 | Issued |
Array
(
[id] => 17660832
[patent_doc_number] => 20220181297
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-09
[patent_title] => Chip Interconnecting Method, Interconnect Device and Method for Forming Chip Packages
[patent_app_type] => utility
[patent_app_number] => 17/542417
[patent_app_country] => US
[patent_app_date] => 2021-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4963
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542417
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/542417 | Chip interconnecting method, interconnect device and method for forming chip packages | Dec 3, 2021 | Issued |
Array
(
[id] => 18408974
[patent_doc_number] => 20230170327
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-01
[patent_title] => INTEGRATED PACKAGING ARCHITECTURE WITH SOLDER AND NON-SOLDER INTERCONNECTS
[patent_app_type] => utility
[patent_app_number] => 17/538603
[patent_app_country] => US
[patent_app_date] => 2021-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17747
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17538603
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/538603 | Integrated packaging architecture with solder and non-solder interconnects | Nov 29, 2021 | Issued |
Array
(
[id] => 18857445
[patent_doc_number] => 11855041
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-26
[patent_title] => Semiconductor package and method of manufacturing semiconductor package
[patent_app_type] => utility
[patent_app_number] => 17/536547
[patent_app_country] => US
[patent_app_date] => 2021-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 21
[patent_no_of_words] => 11051
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 243
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536547
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/536547 | Semiconductor package and method of manufacturing semiconductor package | Nov 28, 2021 | Issued |
Array
(
[id] => 19046735
[patent_doc_number] => 11935855
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-19
[patent_title] => Electronic package structure and method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 17/535407
[patent_app_country] => US
[patent_app_date] => 2021-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4387
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535407
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/535407 | Electronic package structure and method for manufacturing the same | Nov 23, 2021 | Issued |
Array
(
[id] => 17630639
[patent_doc_number] => 20220165654
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-26
[patent_title] => WAFER SYSTEM-LEVEL THREE-DIMENSIONAL FAN-OUT PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/531631
[patent_app_country] => US
[patent_app_date] => 2021-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4501
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531631
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/531631 | Wafer system-level three-dimensional fan-out three-dimensional fan-out packaging structure and manufacturing method thereof | Nov 18, 2021 | Issued |
Array
(
[id] => 17463817
[patent_doc_number] => 20220077123
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-10
[patent_title] => Chip Package Structure and Chip Packaging Method
[patent_app_type] => utility
[patent_app_number] => 17/531133
[patent_app_country] => US
[patent_app_date] => 2021-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12335
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531133
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/531133 | Chip package structure and chip packaging method | Nov 18, 2021 | Issued |
Array
(
[id] => 19370545
[patent_doc_number] => 12062639
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-13
[patent_title] => Semiconductor package and method of fabricating the same
[patent_app_type] => utility
[patent_app_number] => 17/529798
[patent_app_country] => US
[patent_app_date] => 2021-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 7264
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529798
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/529798 | Semiconductor package and method of fabricating the same | Nov 17, 2021 | Issued |
Array
(
[id] => 18379765
[patent_doc_number] => 20230154854
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-18
[patent_title] => Bridge Chip with Through Via
[patent_app_type] => utility
[patent_app_number] => 17/528910
[patent_app_country] => US
[patent_app_date] => 2021-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7343
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17528910
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/528910 | Bridge chip with through via | Nov 16, 2021 | Issued |