Search

Errol V. Fernandes

Examiner (ID: 15300, Phone: (571)270-7433 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2821, 2893
Total Applications
1197
Issued Applications
1012
Pending Applications
72
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18345855 [patent_doc_number] => 20230133965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => Semiconductor Device With Unbalanced Die Stackup [patent_app_type] => utility [patent_app_number] => 17/519261 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519261 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/519261
Semiconductor device with unbalanced die stackup Nov 3, 2021 Issued
Array ( [id] => 19063134 [patent_doc_number] => 11942384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Semiconductor package having an interdigitated mold arrangement [patent_app_type] => utility [patent_app_number] => 17/515234 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3613 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17515234 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/515234
Semiconductor package having an interdigitated mold arrangement Oct 28, 2021 Issued
Array ( [id] => 19796281 [patent_doc_number] => 12237250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/498893 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498893 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/498893
Semiconductor package Oct 11, 2021 Issued
Array ( [id] => 18766984 [patent_doc_number] => 11817394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Semiconductor circuit power delivery [patent_app_type] => utility [patent_app_number] => 17/498472 [patent_app_country] => US [patent_app_date] => 2021-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 9222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 503 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498472 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/498472
Semiconductor circuit power delivery Oct 10, 2021 Issued
Array ( [id] => 17373762 [patent_doc_number] => 20220028814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => SEMICONDUCTOR DEVICE PACKAGES WITH ANGLED PILLARS FOR DECREASING STRESS [patent_app_type] => utility [patent_app_number] => 17/495550 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495550 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495550
Semiconductor device packages with angled pillars for decreasing stress Oct 5, 2021 Issued
Array ( [id] => 19370554 [patent_doc_number] => 12062648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods [patent_app_type] => utility [patent_app_number] => 17/484475 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 52 [patent_no_of_words] => 16232 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17484475 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/484475
Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods Sep 23, 2021 Issued
Array ( [id] => 18761560 [patent_doc_number] => 11812614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Vertical memory devices [patent_app_type] => utility [patent_app_number] => 17/448307 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448307 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448307
Vertical memory devices Sep 20, 2021 Issued
Array ( [id] => 19812384 [patent_doc_number] => 12243797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-03-04 [patent_title] => 3D stack of split graphics processing logic dies [patent_app_type] => utility [patent_app_number] => 17/478843 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 61 [patent_no_of_words] => 31641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17478843 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/478843
3D stack of split graphics processing logic dies Sep 16, 2021 Issued
Array ( [id] => 18481185 [patent_doc_number] => 11694940 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-07-04 [patent_title] => 3D stack of accelerator die and multi-core processor die [patent_app_type] => utility [patent_app_number] => 17/478841 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 61 [patent_no_of_words] => 31553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17478841 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/478841
3D stack of accelerator die and multi-core processor die Sep 16, 2021 Issued
Array ( [id] => 18293606 [patent_doc_number] => 11622489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => 3-D NAND control gate enhancement [patent_app_type] => utility [patent_app_number] => 17/476536 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7275 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476536 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/476536
3-D NAND control gate enhancement Sep 15, 2021 Issued
Array ( [id] => 18967567 [patent_doc_number] => 11901349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Semiconductor packages and methods for forming the same [patent_app_type] => utility [patent_app_number] => 17/475020 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 9031 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17475020 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/475020
Semiconductor packages and methods for forming the same Sep 13, 2021 Issued
Array ( [id] => 18827691 [patent_doc_number] => 11842981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate [patent_app_type] => utility [patent_app_number] => 17/466842 [patent_app_country] => US [patent_app_date] => 2021-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 11804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17466842 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/466842
Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate Sep 2, 2021 Issued
Array ( [id] => 18230267 [patent_doc_number] => 20230069261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DIE ASSEMBLIES WITH DECOMPOSABLE MATERIALS AND ASSOCIATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/463994 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463994 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463994
Semiconductor die assemblies with decomposable materials and associated methods and systems Aug 31, 2021 Issued
Array ( [id] => 18230037 [patent_doc_number] => 20230069031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => Semiconductor Package and Method [patent_app_type] => utility [patent_app_number] => 17/412966 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12113 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412966 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412966
Semiconductor package and method Aug 25, 2021 Issued
Array ( [id] => 18840192 [patent_doc_number] => 11848272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Interconnection between chips by bridge chip [patent_app_type] => utility [patent_app_number] => 17/445161 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 36 [patent_no_of_words] => 11635 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445161 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445161
Interconnection between chips by bridge chip Aug 15, 2021 Issued
Array ( [id] => 17448504 [patent_doc_number] => 20220069009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => CROSS-POINT MAGNETIC RANDOM ACCESS MEMORY WITH PIEZOELECTRIC SELECTOR [patent_app_type] => utility [patent_app_number] => 17/399530 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10416 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399530 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399530
Cross-point magnetic random access memory with piezoelectric selector Aug 10, 2021 Issued
Array ( [id] => 17263141 [patent_doc_number] => 20210376126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => INTEGRATED CIRCUIT DEVICES INCLUDING A VERTICAL FIELD-EFFECT TRANSISTOR (VFET) AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/399118 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399118 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399118
Integrated circuit devices including a vertical field-effect transistor (VFET) and methods of forming the same Aug 10, 2021 Issued
Array ( [id] => 18081110 [patent_doc_number] => 20220406722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => WAFER STACKING STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/396776 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4592 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396776 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396776
Wafer stacking structure and manufacturing method thereof Aug 8, 2021 Issued
Array ( [id] => 18704716 [patent_doc_number] => 11791233 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-17 [patent_title] => Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging [patent_app_type] => utility [patent_app_number] => 17/396585 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 61 [patent_no_of_words] => 31550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396585 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396585
Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging Aug 5, 2021 Issued
Array ( [id] => 17232253 [patent_doc_number] => 20210358810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => FIN FIELD EFFECT TRANSISTOR HAVING AIRGAP AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/389299 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11041 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389299 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/389299
Fin field effect transistor having airgap and method for manufacturing the same Jul 28, 2021 Issued
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