Search

Errol V. Fernandes

Examiner (ID: 15300, Phone: (571)270-7433 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2821, 2893
Total Applications
1197
Issued Applications
1012
Pending Applications
72
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18212361 [patent_doc_number] => 20230058625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => SOLID-STATE IMAGING ELEMENT AND IMAGING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/796896 [patent_app_country] => US [patent_app_date] => 2021-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9930 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17796896 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/796896
SOLID-STATE IMAGING ELEMENT AND IMAGING SYSTEM Feb 1, 2021 Pending
Array ( [id] => 17389405 [patent_doc_number] => 20220037257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => INTEGRATED CIRCUIT (IC) PACKAGE WITH STACKED DIE WIRE BOND CONNECTIONS, AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/158374 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158374 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158374
Integrated circuit (IC) package with stacked die wire bond connections, and related methods Jan 25, 2021 Issued
Array ( [id] => 18798581 [patent_doc_number] => 11832449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/147897 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12523 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147897 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147897
Semiconductor device Jan 12, 2021 Issued
Array ( [id] => 17818745 [patent_doc_number] => 11424370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Non-volatile memory device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/144101 [patent_app_country] => US [patent_app_date] => 2021-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4187 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144101 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/144101
Non-volatile memory device and method for manufacturing the same Jan 6, 2021 Issued
Array ( [id] => 17971381 [patent_doc_number] => 11488930 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-01 [patent_title] => Bonding process with inhibited oxide formation [patent_app_type] => utility [patent_app_number] => 17/138255 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1903 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138255 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138255
Bonding process with inhibited oxide formation Dec 29, 2020 Issued
Array ( [id] => 17700126 [patent_doc_number] => 11373859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Semiconductor substrate singulation systems and related methods [patent_app_type] => utility [patent_app_number] => 17/136243 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 8160 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17136243 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/136243
Semiconductor substrate singulation systems and related methods Dec 28, 2020 Issued
Array ( [id] => 16850582 [patent_doc_number] => 20210151327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => BACK END OF LINE STRUCTURES WITH METAL LINES WITH ALTERNATING PATTERNING AND METALLIZATION SCHEMES [patent_app_type] => utility [patent_app_number] => 17/133919 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133919 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133919
Back end of line structures with metal lines with alternating patterning and metallization schemes Dec 23, 2020 Issued
Array ( [id] => 16765588 [patent_doc_number] => 20210111170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => MICROELECTRONIC ASSEMBLIES [patent_app_type] => utility [patent_app_number] => 17/129134 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17129134 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/129134
Microelectronic assemblies Dec 20, 2020 Issued
Array ( [id] => 16765565 [patent_doc_number] => 20210111147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => MICROELECTRONIC ASSEMBLIES [patent_app_type] => utility [patent_app_number] => 17/126884 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20784 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17126884 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/126884
Microelectronic assemblies Dec 17, 2020 Issued
Array ( [id] => 19444537 [patent_doc_number] => 12094828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Eccentric via structures for stress reduction [patent_app_type] => utility [patent_app_number] => 17/126881 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 6520 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17126881 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/126881
Eccentric via structures for stress reduction Dec 17, 2020 Issued
Array ( [id] => 16782015 [patent_doc_number] => 20210119094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => SEMICONDUCTOR LIGHT EMITTING ELEMENT [patent_app_type] => utility [patent_app_number] => 17/115082 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 495 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115082 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115082
Semiconductor light emitting element Dec 7, 2020 Issued
Array ( [id] => 18169053 [patent_doc_number] => 20230035664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => DISPLAY AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/784541 [patent_app_country] => US [patent_app_date] => 2020-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17784541 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/784541
DISPLAY AND ELECTRONIC DEVICE Nov 25, 2020 Pending
Array ( [id] => 17544149 [patent_doc_number] => 11309283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Packaging structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/099801 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 7517 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17099801 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/099801
Packaging structure and manufacturing method thereof Nov 16, 2020 Issued
Array ( [id] => 16692285 [patent_doc_number] => 20210074764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => 3D VERTICAL MEMORY ARRAY CELL STRUCTURES WITH INDIVIDUAL SELECTORS AND PROCESSES [patent_app_type] => utility [patent_app_number] => 17/099722 [patent_app_country] => US [patent_app_date] => 2020-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17099722 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/099722
3D vertical memory array cell structures with individual selectors and processes Nov 15, 2020 Issued
Array ( [id] => 18047979 [patent_doc_number] => 11521937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Package structures with built-in EMI shielding [patent_app_type] => utility [patent_app_number] => 17/098597 [patent_app_country] => US [patent_app_date] => 2020-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 56 [patent_no_of_words] => 17639 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098597 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/098597
Package structures with built-in EMI shielding Nov 15, 2020 Issued
Array ( [id] => 19260965 [patent_doc_number] => 12021031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Semiconductor package structure [patent_app_type] => utility [patent_app_number] => 17/098659 [patent_app_country] => US [patent_app_date] => 2020-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6082 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098659 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/098659
Semiconductor package structure Nov 15, 2020 Issued
Array ( [id] => 17431789 [patent_doc_number] => 20220059498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => CHIP PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/098436 [patent_app_country] => US [patent_app_date] => 2020-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098436 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/098436
Chip package structure Nov 14, 2020 Issued
Array ( [id] => 19094050 [patent_doc_number] => 11955517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Semiconductor devices including protruding insulation portions between active fins [patent_app_type] => utility [patent_app_number] => 17/098412 [patent_app_country] => US [patent_app_date] => 2020-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 36 [patent_no_of_words] => 7787 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098412 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/098412
Semiconductor devices including protruding insulation portions between active fins Nov 14, 2020 Issued
Array ( [id] => 16677471 [patent_doc_number] => 20210066237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => HIGH-FREQUENCY MODULE [patent_app_type] => utility [patent_app_number] => 17/095940 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095940 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/095940
High-frequency module Nov 11, 2020 Issued
Array ( [id] => 17424487 [patent_doc_number] => 11257951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Method of making semiconductor device having first and second epitaxial materials [patent_app_type] => utility [patent_app_number] => 17/089229 [patent_app_country] => US [patent_app_date] => 2020-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089229 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/089229
Method of making semiconductor device having first and second epitaxial materials Nov 3, 2020 Issued
Menu