Search

Errol V. Fernandes

Examiner (ID: 15300, Phone: (571)270-7433 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2821, 2893
Total Applications
1197
Issued Applications
1012
Pending Applications
72
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17536923 [patent_doc_number] => 20220115532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 17/417677 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17417677 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/417677
Power semiconductor device and manufacturing method therefor Dec 22, 2019 Issued
Array ( [id] => 15807715 [patent_doc_number] => 20200127000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => Surface Topography by Forming Spacer-Like Components [patent_app_type] => utility [patent_app_number] => 16/721565 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721565 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/721565
Surface topography by forming spacer-like components Dec 18, 2019 Issued
Array ( [id] => 15807819 [patent_doc_number] => 20200127052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => MEMORY CELL USING SELECTIVE EPITAXIAL VERTICAL CHANNEL MOS SELECTOR TRANSISTOR [patent_app_type] => utility [patent_app_number] => 16/719790 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719790 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/719790
MEMORY CELL USING SELECTIVE EPITAXIAL VERTICAL CHANNEL MOS SELECTOR TRANSISTOR Dec 17, 2019 Abandoned
Array ( [id] => 15807409 [patent_doc_number] => 20200126847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE HAVING ENHANCED CHARGE TRAPPING EFFICIENCY [patent_app_type] => utility [patent_app_number] => 16/718952 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16718952 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/718952
High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency Dec 17, 2019 Issued
Array ( [id] => 15775797 [patent_doc_number] => 20200118916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/717630 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6135 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717630 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/717630
Semiconductor device and method of manufacturing semiconductor device Dec 16, 2019 Issued
Array ( [id] => 16293546 [patent_doc_number] => 10770401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Method for forming semiconductor device structure with conductive line [patent_app_type] => utility [patent_app_number] => 16/715215 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 30 [patent_no_of_words] => 8628 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715215 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715215
Method for forming semiconductor device structure with conductive line Dec 15, 2019 Issued
Array ( [id] => 17092888 [patent_doc_number] => 11121086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Vertical isolated gate field effect transistor integrated in a semiconductor chip [patent_app_type] => utility [patent_app_number] => 16/716262 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 6466 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16716262 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/716262
Vertical isolated gate field effect transistor integrated in a semiconductor chip Dec 15, 2019 Issued
Array ( [id] => 16888943 [patent_doc_number] => 20210175140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => SEMICONDUCTOR DEVICES AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 16/702854 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16702854 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/702854
Semiconductor devices and related methods Dec 3, 2019 Issued
Array ( [id] => 16609327 [patent_doc_number] => 10910341 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-02 [patent_title] => Bonding process with inhibited oxide formation [patent_app_type] => utility [patent_app_number] => 16/702783 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16702783 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/702783
Bonding process with inhibited oxide formation Dec 3, 2019 Issued
Array ( [id] => 17389541 [patent_doc_number] => 20220037393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => OPTOELECTRONIC DEVICE COMPRISING PIXELS WHICH EMIT THREE COLOURS [patent_app_type] => utility [patent_app_number] => 17/312257 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12942 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17312257 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/312257
Optoelectronic device comprising pixels which emit three colors Dec 2, 2019 Issued
Array ( [id] => 17758117 [patent_doc_number] => 11398416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Package structure and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 16/698973 [patent_app_country] => US [patent_app_date] => 2019-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 7258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16698973 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/698973
Package structure and method of fabricating the same Nov 27, 2019 Issued
Array ( [id] => 15687939 [patent_doc_number] => 20200098633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => FULLY SELF-ALIGNED VIA [patent_app_type] => utility [patent_app_number] => 16/691947 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16691947 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/691947
FULLY SELF-ALIGNED VIA Nov 21, 2019 Abandoned
Array ( [id] => 16752479 [patent_doc_number] => 20210104491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/686995 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16686995 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/686995
Electronic package and method for fabricating the same Nov 17, 2019 Issued
Array ( [id] => 16448370 [patent_doc_number] => 10840301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => 3D vertical memory array cell structures with individual selectors and processes [patent_app_type] => utility [patent_app_number] => 16/687555 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 70 [patent_no_of_words] => 5697 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16687555 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/687555
3D vertical memory array cell structures with individual selectors and processes Nov 17, 2019 Issued
Array ( [id] => 16067909 [patent_doc_number] => 10692919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Solid-state imaging element, imaging device, and electronic device [patent_app_type] => utility [patent_app_number] => 16/686998 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6538 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16686998 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/686998
Solid-state imaging element, imaging device, and electronic device Nov 17, 2019 Issued
Array ( [id] => 17107667 [patent_doc_number] => 11127895 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Magnetic memory device [patent_app_type] => utility [patent_app_number] => 16/684683 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 53 [patent_no_of_words] => 19344 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684683 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684683
Magnetic memory device Nov 14, 2019 Issued
Array ( [id] => 17210777 [patent_doc_number] => 11171154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Vertical memory devices [patent_app_type] => utility [patent_app_number] => 16/684844 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8195 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684844 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684844
Vertical memory devices Nov 14, 2019 Issued
Array ( [id] => 16774005 [patent_doc_number] => 10985126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 16/682084 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682084 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682084
Semiconductor package Nov 12, 2019 Issued
Array ( [id] => 15969943 [patent_doc_number] => 20200168723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => Method for Epitaxial Growth and Device [patent_app_type] => utility [patent_app_number] => 16/682305 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682305 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682305
Method for epitaxial growth and device Nov 12, 2019 Issued
Array ( [id] => 15969427 [patent_doc_number] => 20200168465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => METHOD FOR ETCHING RECESSED STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/675951 [patent_app_country] => US [patent_app_date] => 2019-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16675951 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/675951
Method for etching recessed structures Nov 5, 2019 Issued
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