Search

Errol V. Fernandes

Examiner (ID: 15300, Phone: (571)270-7433 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2821, 2893
Total Applications
1197
Issued Applications
1012
Pending Applications
72
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16660790 [patent_doc_number] => 20210057427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => NON-VOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/672527 [patent_app_country] => US [patent_app_date] => 2019-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16672527 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/672527
Non-volatile memory device and manufacturing method thereof Nov 3, 2019 Issued
Array ( [id] => 16812542 [patent_doc_number] => 20210135097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => Reduce Intermixing on MTJ Sidewall by Oxidation [patent_app_type] => utility [patent_app_number] => 16/672981 [patent_app_country] => US [patent_app_date] => 2019-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16672981 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/672981
Reduce intermixing on MTJ sidewall by oxidation Nov 3, 2019 Issued
Array ( [id] => 16586172 [patent_doc_number] => 20210020574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => Package with Bridge Die For Interconnection and Method Forming Same [patent_app_type] => utility [patent_app_number] => 16/671954 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671954 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/671954
Package with bridge die for interconnection and method forming same Oct 31, 2019 Issued
Array ( [id] => 16812424 [patent_doc_number] => 20210134979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => METHOD FOR FABRICATING GATE STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/670890 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670890 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670890
Method for fabricating gate structures Oct 30, 2019 Issued
Array ( [id] => 17339614 [patent_doc_number] => 20220005945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => COMPOUND SEMICONDUCTOR DEVICE, COMPOUND SEMICONDUCTOR SUBSTRATE, AND METHOD FOR MANUFACTURING COMPOUND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/290145 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17290145 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/290145
Compound semiconductor device, compound semiconductor substrate, and method for manufacturing compound semiconductor device Oct 29, 2019 Issued
Array ( [id] => 15564235 [patent_doc_number] => 20200066529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => DEVICE AND METHOD FOR BONDING OF SUBSTRATES [patent_app_type] => utility [patent_app_number] => 16/667102 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667102 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667102
Device and method for bonding of substrates Oct 28, 2019 Issued
Array ( [id] => 15503567 [patent_doc_number] => 20200051972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => System and Method of Fabricating ESD FinFET With Improved Metal landing in the Drain [patent_app_type] => utility [patent_app_number] => 16/658389 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658389 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/658389
System and method of fabricating ESD FinFET with improved metal landing in the drain Oct 20, 2019 Issued
Array ( [id] => 16803408 [patent_doc_number] => 10998363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Solid-state imaging device and method of producing solid-state imaging device [patent_app_type] => utility [patent_app_number] => 16/655357 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 67 [patent_no_of_words] => 17082 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655357 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/655357
Solid-state imaging device and method of producing solid-state imaging device Oct 16, 2019 Issued
Array ( [id] => 15388939 [patent_doc_number] => 10535668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-14 [patent_title] => Using three or more masks to define contact-line-blocking components in FinFET SRAM fabrication [patent_app_type] => utility [patent_app_number] => 16/654873 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 39 [patent_no_of_words] => 12209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654873 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/654873
Using three or more masks to define contact-line-blocking components in FinFET SRAM fabrication Oct 15, 2019 Issued
Array ( [id] => 15461827 [patent_doc_number] => 20200043738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => Wrap-Around Contact Plug and Method Manufacturing Same [patent_app_type] => utility [patent_app_number] => 16/599773 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599773 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599773
Wrap-around contact plug and method manufacturing same Oct 10, 2019 Issued
Array ( [id] => 16715642 [patent_doc_number] => 20210082789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => SIGNAL ISOLATOR HAVING ENHANCED CREEPAGE CHARACTERISTICS [patent_app_type] => utility [patent_app_number] => 16/574621 [patent_app_country] => US [patent_app_date] => 2019-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4716 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16574621 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/574621
Signal isolator having enhanced creepage characteristics Sep 17, 2019 Issued
Array ( [id] => 16716019 [patent_doc_number] => 20210083166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => SEMICONDUCTOR-SUPERCONDUCTOR HETEROSTRUCTURE [patent_app_type] => utility [patent_app_number] => 16/570745 [patent_app_country] => US [patent_app_date] => 2019-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16570745 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/570745
Semiconductor-superconductor heterostructure Sep 12, 2019 Issued
Array ( [id] => 16699851 [patent_doc_number] => 10950459 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-16 [patent_title] => Back end of line structures with metal lines with alternating patterning and metallization schemes [patent_app_type] => utility [patent_app_number] => 16/570316 [patent_app_country] => US [patent_app_date] => 2019-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16570316 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/570316
Back end of line structures with metal lines with alternating patterning and metallization schemes Sep 12, 2019 Issued
Array ( [id] => 15332177 [patent_doc_number] => 20200006418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => METHOD OF MANUFACTURING AN IMAGER AND IMAGER DEVICE [patent_app_type] => utility [patent_app_number] => 16/566171 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566171 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566171
Method of manufacturing an imager and imager device Sep 9, 2019 Issued
Array ( [id] => 15597629 [patent_doc_number] => 20200075349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => UNDER-FILL DEFLASH FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE [patent_app_type] => utility [patent_app_number] => 16/566844 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566844 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566844
Under-fill deflash for a dual-sided ball grid array package Sep 9, 2019 Issued
Array ( [id] => 15299881 [patent_doc_number] => 20190393076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => DIELECTRIC ISOLATION IN GATE-ALL-AROUND DEVICES [patent_app_type] => utility [patent_app_number] => 16/562098 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562098 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/562098
Dielectric isolation in gate-all-around devices Sep 4, 2019 Issued
Array ( [id] => 15300531 [patent_doc_number] => 20190393401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => FABRICATION OF INTERLAYER DIELECTRICS WITH HIGH QUALITY INTERFACES FOR QUANTUM COMPUTING DEVICES [patent_app_type] => utility [patent_app_number] => 16/557116 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557116 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/557116
Fabrication of interlayer dielectrics with high quality interfaces for quantum computing devices Aug 29, 2019 Issued
Array ( [id] => 15921869 [patent_doc_number] => 10658182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Chip handling and electronic component integration [patent_app_type] => utility [patent_app_number] => 16/551377 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 18230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16551377 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/551377
Chip handling and electronic component integration Aug 25, 2019 Issued
Array ( [id] => 15260149 [patent_doc_number] => 20190378808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => CIRCUIT SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/550402 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550402 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/550402
Circuit substrate Aug 25, 2019 Issued
Array ( [id] => 15259971 [patent_doc_number] => 20190378719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => CHIP HANDLING AND ELECTRONIC COMPONENT INTEGRATION [patent_app_type] => utility [patent_app_number] => 16/550261 [patent_app_country] => US [patent_app_date] => 2019-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550261 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/550261
Chip handling and electronic component integration Aug 24, 2019 Issued
Menu