Search

Errol V. Fernandes

Examiner (ID: 15300, Phone: (571)270-7433 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2821, 2893
Total Applications
1197
Issued Applications
1012
Pending Applications
72
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15077589 [patent_doc_number] => 10468293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels [patent_app_type] => utility [patent_app_number] => 15/857387 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 17176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857387 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857387
Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels Dec 27, 2017 Issued
Array ( [id] => 14542959 [patent_doc_number] => 20190207101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => PHOTOLITHOGRAPHIC METHOD FOR FABRICATING DENSE PILLAR ARRAYS USING SPACERS AS A PATTERN [patent_app_type] => utility [patent_app_number] => 15/857499 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857499 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857499
PHOTOLITHOGRAPHIC METHOD FOR FABRICATING DENSE PILLAR ARRAYS USING SPACERS AS A PATTERN Dec 27, 2017 Abandoned
Array ( [id] => 13173959 [patent_doc_number] => 10103102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Structure and formation method of semiconductor device structure [patent_app_type] => utility [patent_app_number] => 15/855795 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855795 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855795
Structure and formation method of semiconductor device structure Dec 26, 2017 Issued
Array ( [id] => 12849877 [patent_doc_number] => 20180175132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => ORGANIC LIGHT EMITTING DIODE AND ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 15/848820 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15848820 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/848820
ORGANIC LIGHT EMITTING DIODE AND ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME Dec 19, 2017 Abandoned
Array ( [id] => 19679476 [patent_doc_number] => 12191349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Reducing off-state leakage in semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/649287 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 15404 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16649287 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/649287
Reducing off-state leakage in semiconductor devices Dec 14, 2017 Issued
Array ( [id] => 12650838 [patent_doc_number] => 20180108777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => SEMICONDUCTOR DEVICE HAVING FIRST AND SECOND EPITAXIAL MATERIALS [patent_app_type] => utility [patent_app_number] => 15/837546 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837546 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837546
Semiconductor device having first and second epitaxial materials Dec 10, 2017 Issued
Array ( [id] => 12823378 [patent_doc_number] => 20180166298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 15/831811 [patent_app_country] => US [patent_app_date] => 2017-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15831811 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/831811
Substrate processing apparatus Dec 4, 2017 Issued
Array ( [id] => 14412027 [patent_doc_number] => 20190171857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => SEMICONDUCTOR DEVICE AND FINGERPRINT SENSOR DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 15/831813 [patent_app_country] => US [patent_app_date] => 2017-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15831813 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/831813
Semiconductor device and fingerprint sensor device thereof Dec 4, 2017 Issued
Array ( [id] => 12457281 [patent_doc_number] => 09984965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Inductor system and method [patent_app_type] => utility [patent_app_number] => 15/804407 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 30 [patent_no_of_words] => 6096 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804407 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/804407
Inductor system and method Nov 5, 2017 Issued
Array ( [id] => 12573987 [patent_doc_number] => 10020255 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-10 [patent_title] => Integration of super via structure in BEOL [patent_app_type] => utility [patent_app_number] => 15/798794 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6037 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798794 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/798794
Integration of super via structure in BEOL Oct 30, 2017 Issued
Array ( [id] => 12223570 [patent_doc_number] => 20180061930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'Semiconductor Device and Method for Forming Same' [patent_app_type] => utility [patent_app_number] => 15/790614 [patent_app_country] => US [patent_app_date] => 2017-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15790614 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/790614
Semiconductor device and method for forming same Oct 22, 2017 Issued
Array ( [id] => 12181619 [patent_doc_number] => 20180040554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH STACKED ANALOG COMPONENTS IN BACK END OF LINE (BEOL) REGIONS' [patent_app_type] => utility [patent_app_number] => 15/785931 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2478 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785931 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/785931
Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions Oct 16, 2017 Issued
Array ( [id] => 12631323 [patent_doc_number] => 20180102271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/782249 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 42480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782249 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/782249
Method for manufacturing semiconductor device Oct 11, 2017 Issued
Array ( [id] => 12919912 [patent_doc_number] => 20180198480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => DISPLAY PANEL WITH TRANSPARENT CONDUCTOR BASED ISOLATOR AND METHOD FOR IMPROVED WIRELESS COMMUNICATIONS [patent_app_type] => utility [patent_app_number] => 15/730333 [patent_app_country] => US [patent_app_date] => 2017-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15730333 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/730333
Display panel with transparent conductor based isolator and method for improved wireless communications Oct 10, 2017 Issued
Array ( [id] => 13071031 [patent_doc_number] => 10056300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Methods of forming NMOS and PMOS finFET devices and the resulting product [patent_app_type] => utility [patent_app_number] => 15/729051 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 5863 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15729051 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/729051
Methods of forming NMOS and PMOS finFET devices and the resulting product Oct 9, 2017 Issued
Array ( [id] => 14920399 [patent_doc_number] => 10431526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Rivetless lead fastening for a semiconductor package [patent_app_type] => utility [patent_app_number] => 15/727725 [patent_app_country] => US [patent_app_date] => 2017-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7160 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15727725 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/727725
Rivetless lead fastening for a semiconductor package Oct 8, 2017 Issued
Array ( [id] => 14163875 [patent_doc_number] => 20190109040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => DIELECTRIC ISOLATION IN GATE-ALL-AROUND DEVICES [patent_app_type] => utility [patent_app_number] => 15/727974 [patent_app_country] => US [patent_app_date] => 2017-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15727974 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/727974
Dielectric isolation in gate-all-around devices Oct 8, 2017 Issued
Array ( [id] => 12573984 [patent_doc_number] => 10020254 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-10 [patent_title] => Integration of super via structure in BEOL [patent_app_type] => utility [patent_app_number] => 15/727956 [patent_app_country] => US [patent_app_date] => 2017-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6007 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15727956 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/727956
Integration of super via structure in BEOL Oct 8, 2017 Issued
Array ( [id] => 15427665 [patent_doc_number] => 10546771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency [patent_app_type] => utility [patent_app_number] => 15/727723 [patent_app_country] => US [patent_app_date] => 2017-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 12547 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15727723 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/727723
High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency Oct 8, 2017 Issued
Array ( [id] => 18105519 [patent_doc_number] => 11545416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Minimization of insertion loss variation in through-silicon vias (TSVs) [patent_app_type] => utility [patent_app_number] => 16/643816 [patent_app_country] => US [patent_app_date] => 2017-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7996 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16643816 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/643816
Minimization of insertion loss variation in through-silicon vias (TSVs) Sep 29, 2017 Issued
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