Search

Errol V. Fernandes

Examiner (ID: 15300, Phone: (571)270-7433 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2821, 2893
Total Applications
1197
Issued Applications
1012
Pending Applications
72
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16936552 [patent_doc_number] => 20210202441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => SYSTEM AND METHOD FOR STACKING WIRE-BOND CONVERTED FLIP-CHIP DIE [patent_app_type] => utility [patent_app_number] => 16/070510 [patent_app_country] => US [patent_app_date] => 2016-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16070510 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/070510
SYSTEM AND METHOD FOR STACKING WIRE-BOND CONVERTED FLIP-CHIP DIE Feb 4, 2016 Abandoned
Array ( [id] => 11096521 [patent_doc_number] => 20160293490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'Integrated High-K/Metal Gate in CMOS Process Flow' [patent_app_type] => utility [patent_app_number] => 15/010306 [patent_app_country] => US [patent_app_date] => 2016-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 8155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15010306 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/010306
Integrated high-K/metal gate in CMOS process flow Jan 28, 2016 Issued
Array ( [id] => 10795145 [patent_doc_number] => 20160141302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/007404 [patent_app_country] => US [patent_app_date] => 2016-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7055 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15007404 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/007404
Semiconductor device and method of manufacturing the same Jan 26, 2016 Issued
Array ( [id] => 11673888 [patent_doc_number] => 20170162612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'Preparation Method of Oxide Thin-Film Transistor' [patent_app_type] => utility [patent_app_number] => 15/308991 [patent_app_country] => US [patent_app_date] => 2016-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8110 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15308991 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/308991
Preparation method of oxide thin-film transistor Jan 24, 2016 Issued
Array ( [id] => 11652918 [patent_doc_number] => 20170148819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'PREPARATION METHOD OF CONDUCTIVE VIA HOLE STRUCTURE, ARRAY SUBSTRATE AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/114219 [patent_app_country] => US [patent_app_date] => 2016-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9084 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15114219 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/114219
Preparation method of conductive via hole structure, array substrate and display device Jan 20, 2016 Issued
Array ( [id] => 11710943 [patent_doc_number] => 20170179442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'MASK GROUP AND METHOD FOR FABRICATING AN ORGANIC LUMINESCENCE LAYER, DISPLAY PANEL AND DRIVING METHOD' [patent_app_type] => utility [patent_app_number] => 15/129626 [patent_app_country] => US [patent_app_date] => 2016-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4241 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15129626 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/129626
Mask group and method for fabricating an organic luminescence layer, display panel and driving method Jan 13, 2016 Issued
Array ( [id] => 11710943 [patent_doc_number] => 20170179442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'MASK GROUP AND METHOD FOR FABRICATING AN ORGANIC LUMINESCENCE LAYER, DISPLAY PANEL AND DRIVING METHOD' [patent_app_type] => utility [patent_app_number] => 15/129626 [patent_app_country] => US [patent_app_date] => 2016-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4241 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15129626 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/129626
Mask group and method for fabricating an organic luminescence layer, display panel and driving method Jan 13, 2016 Issued
Array ( [id] => 11787757 [patent_doc_number] => 09397227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Split gate flash cell semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/993821 [patent_app_country] => US [patent_app_date] => 2016-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14993821 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/993821
Split gate flash cell semiconductor device Jan 11, 2016 Issued
Array ( [id] => 16668480 [patent_doc_number] => 10937738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Semiconductor package and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 14/991800 [patent_app_country] => US [patent_app_date] => 2016-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 11247 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14991800 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/991800
Semiconductor package and method of manufacturing the same Jan 7, 2016 Issued
Array ( [id] => 14801593 [patent_doc_number] => 10403808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Fabrication of interlayer dielectrics with high quality interfaces for quantum computing devices [patent_app_type] => utility [patent_app_number] => 16/066640 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6178 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16066640 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/066640
Fabrication of interlayer dielectrics with high quality interfaces for quantum computing devices Dec 29, 2015 Issued
Array ( [id] => 10617801 [patent_doc_number] => 09337252 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-10 [patent_title] => 'Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions' [patent_app_type] => utility [patent_app_number] => 14/982061 [patent_app_country] => US [patent_app_date] => 2015-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 2467 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14982061 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/982061
Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions Dec 28, 2015 Issued
Array ( [id] => 12293856 [patent_doc_number] => 09934973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Method for obtaining patterns in a layer [patent_app_type] => utility [patent_app_number] => 15/538564 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 39 [patent_no_of_words] => 11380 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15538564 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/538564
Method for obtaining patterns in a layer Dec 21, 2015 Issued
Array ( [id] => 15475103 [patent_doc_number] => 10553435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Method for obtaining patterns in a layer [patent_app_type] => utility [patent_app_number] => 15/538526 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 9805 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15538526 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/538526
Method for obtaining patterns in a layer Dec 21, 2015 Issued
Array ( [id] => 10765248 [patent_doc_number] => 20160111404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES' [patent_app_type] => utility [patent_app_number] => 14/977214 [patent_app_country] => US [patent_app_date] => 2015-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11289 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977214 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977214
Methods of forming 3-D circuits with integrated passive devices Dec 20, 2015 Issued
Array ( [id] => 11831929 [patent_doc_number] => 09728679 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Optoelectronic device and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 14/971046 [patent_app_country] => US [patent_app_date] => 2015-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 23 [patent_no_of_words] => 8510 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14971046 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/971046
Optoelectronic device and method for manufacturing same Dec 15, 2015 Issued
Array ( [id] => 10753181 [patent_doc_number] => 20160099333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION' [patent_app_type] => utility [patent_app_number] => 14/967797 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967797 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/967797
FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION Dec 13, 2015 Abandoned
Array ( [id] => 11198488 [patent_doc_number] => 09428691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Semiconductor structure having nanocrystalline core and nanocrystalline shell pairing with compositional transition layer' [patent_app_type] => utility [patent_app_number] => 14/967162 [patent_app_country] => US [patent_app_date] => 2015-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 16728 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967162 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/967162
Semiconductor structure having nanocrystalline core and nanocrystalline shell pairing with compositional transition layer Dec 10, 2015 Issued
Array ( [id] => 10740902 [patent_doc_number] => 20160087054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'Self-Aligned Wrapped-Around Structure' [patent_app_type] => utility [patent_app_number] => 14/961691 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14961691 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/961691
Self-aligned wrapped-around structure Dec 6, 2015 Issued
Array ( [id] => 13228709 [patent_doc_number] => 10128135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Heat treatment method and heat treatment device [patent_app_type] => utility [patent_app_number] => 15/560047 [patent_app_country] => US [patent_app_date] => 2015-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 11816 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15560047 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/560047
Heat treatment method and heat treatment device Nov 17, 2015 Issued
Array ( [id] => 10597544 [patent_doc_number] => 09318641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Nanowires formed by employing solder nanodots' [patent_app_type] => utility [patent_app_number] => 14/944741 [patent_app_country] => US [patent_app_date] => 2015-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4666 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14944741 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/944741
Nanowires formed by employing solder nanodots Nov 17, 2015 Issued
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